📄 data_read_40bit.vhd
字号:
DPRA0 => fifo20_rd_addr_r(0),
DPRA1 => fifo20_rd_addr_r(1),
DPRA2 => fifo20_rd_addr_r(2),
DPRA3 => fifo20_rd_addr_r(3),
WCLK => dqs2_delayed_col1_n,
WE => fifo_21_wr_en );
fifo0_bit19 : RAM16X1D
port map (DPO => fifo_20_data_out(3),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(19),
DPRA0 => fifo21_rd_addr_r(0),
DPRA1 => fifo21_rd_addr_r(1),
DPRA2 => fifo21_rd_addr_r(2),
DPRA3 => fifo21_rd_addr_r(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit19 : RAM16X1D
port map (DPO => fifo_21_data_out(3),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(19),
DPRA0 => fifo21_rd_addr_r(0),
DPRA1 => fifo21_rd_addr_r(1),
DPRA2 => fifo21_rd_addr_r(2),
DPRA3 => fifo21_rd_addr_r(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit20 : RAM16X1D
port map (DPO => fifo_20_data_out(4),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(20),
DPRA0 => fifo20_rd_addr_r(0),
DPRA1 => fifo20_rd_addr_r(1),
DPRA2 => fifo20_rd_addr_r(2),
DPRA3 => fifo20_rd_addr_r(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit20 : RAM16X1D
port map (DPO => fifo_21_data_out(4),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(20),
DPRA0 => fifo20_rd_addr_r(0),
DPRA1 => fifo20_rd_addr_r(1),
DPRA2 => fifo20_rd_addr_r(2),
DPRA3 => fifo20_rd_addr_r(3),
WCLK => dqs2_delayed_col1_n,
WE => fifo_21_wr_en );
fifo0_bit21 : RAM16X1D
port map (DPO => fifo_20_data_out(5),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(21),
DPRA0 => fifo21_rd_addr_r(0),
DPRA1 => fifo21_rd_addr_r(1),
DPRA2 => fifo21_rd_addr_r(2),
DPRA3 => fifo21_rd_addr_r(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit21 : RAM16X1D
port map (DPO => fifo_21_data_out(5),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(21),
DPRA0 => fifo21_rd_addr_r(0),
DPRA1 => fifo21_rd_addr_r(1),
DPRA2 => fifo21_rd_addr_r(2),
DPRA3 => fifo21_rd_addr_r(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit22 : RAM16X1D
port map (DPO => fifo_20_data_out(6),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(22),
DPRA0 => fifo20_rd_addr_r(0),
DPRA1 => fifo20_rd_addr_r(1),
DPRA2 => fifo20_rd_addr_r(2),
DPRA3 => fifo20_rd_addr_r(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit22 : RAM16X1D
port map (DPO => fifo_21_data_out(6),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(22),
DPRA0 => fifo20_rd_addr_r(0),
DPRA1 => fifo20_rd_addr_r(1),
DPRA2 => fifo20_rd_addr_r(2),
DPRA3 => fifo20_rd_addr_r(3),
WCLK => dqs2_delayed_col1_n,
WE => fifo_21_wr_en );
fifo0_bit23 : RAM16X1D
port map (DPO => fifo_20_data_out(7),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(23),
DPRA0 => fifo21_rd_addr_r(0),
DPRA1 => fifo21_rd_addr_r(1),
DPRA2 => fifo21_rd_addr_r(2),
DPRA3 => fifo21_rd_addr_r(3),
WCLK => dqs2_delayed_col0,
WE => fifo_20_wr_en );
fifo1_bit23 : RAM16X1D
port map (DPO => fifo_21_data_out(7),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(23),
DPRA0 => fifo21_rd_addr_r(0),
DPRA1 => fifo21_rd_addr_r(1),
DPRA2 => fifo21_rd_addr_r(2),
DPRA3 => fifo21_rd_addr_r(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
--Byte3 Fifo Instantiation
fifo0_bit24 : RAM16X1D
port map (DPO => fifo_30_data_out(0),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(24),
DPRA0 => fifo30_rd_addr_r(0),
DPRA1 => fifo30_rd_addr_r(1),
DPRA2 => fifo30_rd_addr_r(2),
DPRA3 => fifo30_rd_addr_r(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit24 : RAM16X1D
port map (DPO => fifo_31_data_out(0),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(24),
DPRA0 => fifo30_rd_addr_r(0),
DPRA1 => fifo30_rd_addr_r(1),
DPRA2 => fifo30_rd_addr_r(2),
DPRA3 => fifo30_rd_addr_r(3),
WCLK => dqs3_delayed_col1_n,
WE => fifo_31_wr_en );
fifo0_bit25 : RAM16X1D
port map (DPO => fifo_30_data_out(1),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(25),
DPRA0 => fifo31_rd_addr_r(0),
DPRA1 => fifo31_rd_addr_r(1),
DPRA2 => fifo31_rd_addr_r(2),
DPRA3 => fifo31_rd_addr_r(3),
WCLK => dqs3_delayed_col0,
WE => fifo_30_wr_en );
fifo1_bit25 : RAM16X1D
port map (DPO => fifo_31_data_out(1),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(25),
DPRA0 => fifo31_rd_addr_r(0),
DPRA1 => fifo31_rd_addr_r(1),
DPRA2 => fifo31_rd_addr_r(2),
DPRA3 => fifo31_rd_addr_r(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit26 : RAM16X1D
port map (DPO => fifo_30_data_out(2),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo30_rd_addr_r(0),
DPRA1 => fifo30_rd_addr_r(1),
DPRA2 => fifo30_rd_addr_r(2),
DPRA3 => fifo30_rd_addr_r(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit26 : RAM16X1D
port map (DPO => fifo_31_data_out(2),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(26),
DPRA0 => fifo30_rd_addr_r(0),
DPRA1 => fifo30_rd_addr_r(1),
DPRA2 => fifo30_rd_addr_r(2),
DPRA3 => fifo30_rd_addr_r(3),
WCLK => dqs3_delayed_col1_n,
WE => fifo_31_wr_en );
fifo0_bit27 : RAM16X1D
port map (DPO => fifo_30_data_out(3),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(27),
DPRA0 => fifo31_rd_addr_r(0),
DPRA1 => fifo31_rd_addr_r(1),
DPRA2 => fifo31_rd_addr_r(2),
DPRA3 => fifo31_rd_addr_r(3),
WCLK => dqs3_delayed_col0,
WE => fifo_30_wr_en );
fifo1_bit27 : RAM16X1D
port map (DPO => fifo_31_data_out(3),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(27),
DPRA0 => fifo31_rd_addr_r(0),
DPRA1 => fifo31_rd_addr_r(1),
DPRA2 => fifo31_rd_addr_r(2),
DPRA3 => fifo31_rd_addr_r(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit28 : RAM16X1D
port map (DPO => fifo_30_data_out(4),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(28),
DPRA0 => fifo30_rd_addr_r(0),
DPRA1 => fifo30_rd_addr_r(1),
DPRA2 => fifo30_rd_addr_r(2),
DPRA3 => fifo30_rd_addr_r(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit28 : RAM16X1D
port map (DPO => fifo_31_data_out(4),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(28),
DPRA0 => fifo30_rd_addr_r(0),
DPRA1 => fifo30_rd_addr_r(1),
DPRA2 => fifo30_rd_addr_r(2),
DPRA3 => fifo30_rd_addr_r(3),
WCLK => dqs3_delayed_col1_n,
WE => fifo_31_wr_en );
fifo0_bit29 : RAM16X1D
port map (DPO => fifo_30_data_out(5),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(29),
DPRA0 => fifo31_rd_addr_r(0),
DPRA1 => fifo31_rd_addr_r(1),
DPRA2 => fifo31_rd_addr_r(2),
DPRA3 => fifo31_rd_addr_r(3),
WCLK => dqs3_delayed_col0,
WE => fifo_30_wr_en );
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -