data_write_40bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*********************************************************************
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in 
-- the data capture

-- in the current architecture data ( dq ) from ddr memory 
-- directly stored into the FIFO's.

-- Architectural changes :

-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs 

-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed 
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed 
-- data valid signals registering in clk90 domain was removed

-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
-- write enable for the FIFOs derived from rst_dqs_div signal


-- Code revised by 	: Narayana Murty.
-- Date 			      : Nov 18, 2003. 

--*********************************************************************


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--use work.parameter_40bit.all;

entity   data_write_40bit  is
port(
     user_input_data    : in std_logic_vector(79 downto 0);
     user_data_mask     : in std_logic_vector(9 downto 0);
     clk90              : in std_logic;
     reset90_r          : in std_logic;
     reset270_r         : in std_logic;
     write_enable       : in std_logic;
     write_en_val       : out std_logic;
     write_data_falling : out std_logic_vector(39 downto 0);
     write_data_rising  : out std_logic_vector(39 downto 0);
     data_mask_f        : out std_logic_vector(4 downto 0);
     data_mask_r        : out std_logic_vector(4 downto 0)
     );
end   data_write_40bit;  

architecture   arc_data_write_40bit of   data_write_40bit    is
component FD
   port(
      Q                              :  out   STD_LOGIC;
      D                              :  in    STD_LOGIC;
      C                              :  in    STD_LOGIC);
end component;

signal write_en_P1            : std_logic;
signal write_en_P2            : std_logic;
signal write_en_P3            : std_logic;
signal write_en_int           : std_logic;
signal write_data             : std_logic_vector(79 downto 0);
signal write_data1            : std_logic_vector(79 downto 0);
signal write_data2            : std_logic_vector(79 downto 0);
signal write_data3            : std_logic_vector(79 downto 0);
signal write_data4            : std_logic_vector(79 downto 0);
signal write_data5            : std_logic_vector(79 downto 0);
signal write_data6            : std_logic_vector(79 downto 0);
signal write_data_int         : std_logic_vector(79 downto 0);
signal write_data270_1        : std_logic_vector(39 downto 0);
signal write_data270_2        : std_logic_vector(39 downto 0);


signal write_data_m             : std_logic_vector(9 downto 0);
signal write_data_m1            : std_logic_vector(9 downto 0);
signal write_data_m2            : std_logic_vector(9 downto 0);
signal write_data_m3            : std_logic_vector(9 downto 0);
signal write_data_m4            : std_logic_vector(9 downto 0);
signal write_data_m5            : std_logic_vector(9 downto 0);
signal write_data_m6            : std_logic_vector(9 downto 0);
signal write_data_mask          : std_logic_vector(9 downto 0);
signal write_data_m270_1        : std_logic_vector(4 downto 0);
signal write_data_m270_2        : std_logic_vector(4 downto 0);



begin

--data_mask_f <= "00000";
--data_mask_r <= "00000";

-- data path for write enable
process(clk90)
begin
  if clk90'event and clk90 = '1' then 
   if reset90_r = '1' then
    write_en_P1 <= '0';
    write_en_P2 <= '0';
    write_en_P3 <= '0';
   else 
     write_en_P1 <= write_enable;
     write_en_P2 <= write_en_P1;
     write_en_P3 <= write_en_P2;
   end if;  
  end if;
end process;

-- data path for write enable
process(clk90)
begin
 if clk90'event and clk90 = '0' then
  if reset90_r = '1' then
    write_en_int    <= '0';
    write_en_val    <= '0';
  
  else
     write_en_int   <= write_en_P2;
--     write_en_val   <= write_en_int;
--       write_en_val   <= write_enable;
     write_en_val   <= write_en_P1;

   
  end if;
 end if;
end process;


-- pipeline varables

process(clk90)
begin
  if clk90'event and clk90 = '0' then
-- varable_in
  end if;
end process;

write_data_rising  <= write_data270_2;
write_data_falling <= write_data(39 downto 0);

data_mask_r <= write_data_m270_2;
data_mask_f <= write_data_mask(4 downto 0);


end   arc_data_write_40bit;