📄 data_read_32bit.vhd
字号:
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(5),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit6 : RAM16X1D
port map (DPO => fifo_10_data_out(2),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(6),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col1,
WE => fifo_10_wr_en );
fifo1_bit6 : RAM16X1D
port map (DPO => fifo_11_data_out(2),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(6),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit7 : RAM16X1D
port map (DPO => fifo_10_data_out(3),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(7),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col1,
WE => fifo_10_wr_en );
fifo1_bit7 : RAM16X1D
port map (DPO => fifo_11_data_out(3),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(7),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
--- Nibble2 instantiation
fifo0_bit8 : RAM16X1D
port map (DPO => fifo_20_data_out(0),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(8),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit8 : RAM16X1D
port map (DPO => fifo_21_data_out(0),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(8),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit9 : RAM16X1D
port map (DPO => fifo_20_data_out(1),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(9),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit9 : RAM16X1D
port map (DPO => fifo_21_data_out(1),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(9),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit10 : RAM16X1D
port map (DPO => fifo_20_data_out(2),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(10),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit10 : RAM16X1D
port map (DPO => fifo_21_data_out(2),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(10),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
fifo0_bit11 : RAM16X1D
port map (DPO => fifo_20_data_out(3),
A0 => fifo_20_wr_addr(0),
A1 => fifo_20_wr_addr(1),
A2 => fifo_20_wr_addr(2),
A3 => fifo_20_wr_addr(3),
D => ddr_dq_in(11),
DPRA0 => fifo_20_rd_addr(0),
DPRA1 => fifo_20_rd_addr(1),
DPRA2 => fifo_20_rd_addr(2),
DPRA3 => fifo_20_rd_addr(3),
WCLK => dqs2_delayed_col1,
WE => fifo_20_wr_en );
fifo1_bit11 : RAM16X1D
port map (DPO => fifo_21_data_out(3),
A0 => fifo_21_wr_addr(0),
A1 => fifo_21_wr_addr(1),
A2 => fifo_21_wr_addr(2),
A3 => fifo_21_wr_addr(3),
D => ddr_dq_in(11),
DPRA0 => fifo_21_rd_addr(0),
DPRA1 => fifo_21_rd_addr(1),
DPRA2 => fifo_21_rd_addr(2),
DPRA3 => fifo_21_rd_addr(3),
WCLK => dqs2_delayed_col0_n,
WE => fifo_21_wr_en );
--- Nibble3 instantiation
fifo0_bit12 : RAM16X1D
port map (DPO => fifo_30_data_out(0),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(12),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit12 : RAM16X1D
port map (DPO => fifo_31_data_out(0),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(12),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit13 : RAM16X1D
port map (DPO => fifo_30_data_out(1),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(13),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit13 : RAM16X1D
port map (DPO => fifo_31_data_out(1),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(13),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit14 : RAM16X1D
port map (DPO => fifo_30_data_out(2),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(14),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit14 : RAM16X1D
port map (DPO => fifo_31_data_out(2),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(14),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
fifo0_bit15 : RAM16X1D
port map (DPO => fifo_30_data_out(3),
A0 => fifo_30_wr_addr(0),
A1 => fifo_30_wr_addr(1),
A2 => fifo_30_wr_addr(2),
A3 => fifo_30_wr_addr(3),
D => ddr_dq_in(15),
DPRA0 => fifo_30_rd_addr(0),
DPRA1 => fifo_30_rd_addr(1),
DPRA2 => fifo_30_rd_addr(2),
DPRA3 => fifo_30_rd_addr(3),
WCLK => dqs3_delayed_col1,
WE => fifo_30_wr_en );
fifo1_bit15 : RAM16X1D
port map (DPO => fifo_31_data_out(3),
A0 => fifo_31_wr_addr(0),
A1 => fifo_31_wr_addr(1),
A2 => fifo_31_wr_addr(2),
A3 => fifo_31_wr_addr(3),
D => ddr_dq_in(15),
DPRA0 => fifo_31_rd_addr(0),
DPRA1 => fifo_31_rd_addr(1),
DPRA2 => fifo_31_rd_addr(2),
DPRA3 => fifo_31_rd_addr(3),
WCLK => dqs3_delayed_col0_n,
WE => fifo_31_wr_en );
--Nibble4 Fifo instantiation
fifo0_bit16 : RAM16X1D
port map (DPO => fifo_40_data_out(0),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(16),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit16 : RAM16X1D
port map (DPO => fifo_41_data_out(0),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(16),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit17 : RAM16X1D
port map (DPO => fifo_40_data_out(1),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(17),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit17 : RAM16X1D
port map (DPO => fifo_41_data_out(1),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(17),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
DPRA2 => fifo_41_rd_addr(2),
DPRA3 => fifo_41_rd_addr(3),
WCLK => dqs4_delayed_col0_n,
WE => fifo_41_wr_en );
fifo0_bit18 : RAM16X1D
port map (DPO => fifo_40_data_out(2),
A0 => fifo_40_wr_addr(0),
A1 => fifo_40_wr_addr(1),
A2 => fifo_40_wr_addr(2),
A3 => fifo_40_wr_addr(3),
D => ddr_dq_in(18),
DPRA0 => fifo_40_rd_addr(0),
DPRA1 => fifo_40_rd_addr(1),
DPRA2 => fifo_40_rd_addr(2),
DPRA3 => fifo_40_rd_addr(3),
WCLK => dqs4_delayed_col1,
WE => fifo_40_wr_en );
fifo1_bit18 : RAM16X1D
port map (DPO => fifo_41_data_out(2),
A0 => fifo_41_wr_addr(0),
A1 => fifo_41_wr_addr(1),
A2 => fifo_41_wr_addr(2),
A3 => fifo_41_wr_addr(3),
D => ddr_dq_in(18),
DPRA0 => fifo_41_rd_addr(0),
DPRA1 => fifo_41_rd_addr(1),
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