📄 data_read_32bit.vhd
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--*********************************************************************
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins
-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in
-- the data capture
-- in the current architecture data ( dq ) from ddr memory
-- directly stored into the FIFO's.
-- Architectural changes :
-- Used only TWO FIFOs ( instead of FOUR FIFOs )
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs
-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed
-- data valid signals registering in clk90 domain was removed
-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic
-- write enable for the FIFOs derived from rst_dqs_div signal
-- Code revised by : Narayana Murty.
-- Date : Nov 18, 2003.
--*********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity data_read_32bit is
port(
clk : in std_logic;
clk90 : in std_logic;
reset90_r : in std_logic;
reset270_r : in std_logic;
ddr_dq_in : in std_logic_vector(31 downto 0);
read_valid_data_1 : in std_logic;
fifo_00_wr_en : in std_logic;
fifo_10_wr_en : in std_logic;
fifo_20_wr_en : in std_logic;
fifo_30_wr_en : in std_logic;
fifo_40_wr_en : in std_logic;
fifo_50_wr_en : in std_logic;
fifo_60_wr_en : in std_logic;
fifo_70_wr_en : in std_logic;
fifo_01_wr_en : in std_logic;
fifo_11_wr_en : in std_logic;
fifo_21_wr_en : in std_logic;
fifo_31_wr_en : in std_logic;
fifo_41_wr_en : in std_logic;
fifo_51_wr_en : in std_logic;
fifo_61_wr_en : in std_logic;
fifo_71_wr_en : in std_logic;
fifo_00_wr_addr : in std_logic_vector(3 downto 0);
fifo_01_wr_addr : in std_logic_vector(3 downto 0);
fifo_10_wr_addr : in std_logic_vector(3 downto 0);
fifo_11_wr_addr : in std_logic_vector(3 downto 0);
fifo_20_wr_addr : in std_logic_vector(3 downto 0);
fifo_21_wr_addr : in std_logic_vector(3 downto 0);
fifo_30_wr_addr : in std_logic_vector(3 downto 0);
fifo_31_wr_addr : in std_logic_vector(3 downto 0);
fifo_40_wr_addr : in std_logic_vector(3 downto 0);
fifo_41_wr_addr : in std_logic_vector(3 downto 0);
fifo_50_wr_addr : in std_logic_vector(3 downto 0);
fifo_51_wr_addr : in std_logic_vector(3 downto 0);
fifo_60_wr_addr : in std_logic_vector(3 downto 0);
fifo_61_wr_addr : in std_logic_vector(3 downto 0);
fifo_70_wr_addr : in std_logic_vector(3 downto 0);
fifo_71_wr_addr : in std_logic_vector(3 downto 0);
dqs0_delayed_col0 : in std_logic;
dqs1_delayed_col0 : in std_logic;
dqs2_delayed_col0 : in std_logic;
dqs3_delayed_col0 : in std_logic;
dqs4_delayed_col0 : in std_logic;
dqs5_delayed_col0 : in std_logic;
dqs6_delayed_col0 : in std_logic;
dqs7_delayed_col0 : in std_logic;
dqs0_delayed_col0_n: in std_logic;
dqs1_delayed_col0_n: in std_logic;
dqs2_delayed_col0_n: in std_logic;
dqs3_delayed_col0_n: in std_logic;
dqs4_delayed_col0_n: in std_logic;
dqs5_delayed_col0_n: in std_logic;
dqs6_delayed_col0_n: in std_logic;
dqs7_delayed_col0_n: in std_logic;
user_output_data : out std_logic_vector(63 downto 0);
fifo_00_rd_addr : in std_logic_vector(3 downto 0);
fifo_01_rd_addr : in std_logic_vector(3 downto 0);
fifo_10_rd_addr : in std_logic_vector(3 downto 0);
fifo_11_rd_addr : in std_logic_vector(3 downto 0);
fifo_20_rd_addr : in std_logic_vector(3 downto 0);
fifo_21_rd_addr : in std_logic_vector(3 downto 0);
fifo_30_rd_addr : in std_logic_vector(3 downto 0);
fifo_31_rd_addr : in std_logic_vector(3 downto 0);
fifo_40_rd_addr : in std_logic_vector(3 downto 0);
fifo_41_rd_addr : in std_logic_vector(3 downto 0);
fifo_50_rd_addr : in std_logic_vector(3 downto 0);
fifo_51_rd_addr : in std_logic_vector(3 downto 0);
fifo_60_rd_addr : in std_logic_vector(3 downto 0);
fifo_61_rd_addr : in std_logic_vector(3 downto 0);
fifo_70_rd_addr : in std_logic_vector(3 downto 0);
fifo_71_rd_addr : in std_logic_vector(3 downto 0)
);
end data_read_32bit;
architecture arc_data_read_32bit of data_read_32bit is
attribute syn_keep : boolean; -- Using Syn_Keep Derictive
component FD port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
-- 16x1 Dual Port RAM Component Instansiated
component RAM16X1D
port (D : in std_logic;
WE : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
SPO : out std_logic;
DPO : out std_logic);
end component;
signal fifo_00_data_out : std_logic_vector(3 downto 0);
signal fifo_01_data_out : std_logic_vector(3 downto 0);
signal fifo_10_data_out : std_logic_vector(3 downto 0);
signal fifo_11_data_out : std_logic_vector(3 downto 0);
signal fifo_20_data_out : std_logic_vector(3 downto 0);
signal fifo_21_data_out : std_logic_vector(3 downto 0);
signal fifo_30_data_out : std_logic_vector(3 downto 0);
signal fifo_31_data_out : std_logic_vector(3 downto 0);
signal fifo_40_data_out : std_logic_vector(3 downto 0);
signal fifo_41_data_out : std_logic_vector(3 downto 0);
signal fifo_50_data_out : std_logic_vector(3 downto 0);
signal fifo_51_data_out : std_logic_vector(3 downto 0);
signal fifo_60_data_out : std_logic_vector(3 downto 0);
signal fifo_61_data_out : std_logic_vector(3 downto 0);
signal fifo_70_data_out : std_logic_vector(3 downto 0);
signal fifo_71_data_out : std_logic_vector(3 downto 0);
signal first_sdr_data : std_logic_vector(63 downto 0);
begin
user_output_data <= first_sdr_data;
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
first_sdr_data <= (others => '0');
else
if (read_valid_data_1 = '1') then
first_sdr_data <=
fifo_70_data_out &
fifo_60_data_out & fifo_50_data_out & fifo_40_data_out &
fifo_30_data_out & fifo_20_data_out & fifo_10_data_out &
fifo_00_data_out & fifo_71_data_out &
fifo_61_data_out & fifo_51_data_out & fifo_41_data_out &
fifo_31_data_out & fifo_21_data_out & fifo_11_data_out &
fifo_01_data_out;
else
first_sdr_data <= first_sdr_data;
end if;
end if;
end if;
end process;
--*************************************************************************************************************************
-- Dual Port RAM 16x1 instantiations (fifo0 -- Positive edge, fifo1 -- Trailing edge)
--*************************************************************************************************************************
--- Nibble0 instantiation
fifo0_bit0 : RAM16X1D
port map (DPO => fifo_00_data_out(0),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(0),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit0 : RAM16X1D
port map (DPO => fifo_01_data_out(0),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(0),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit1 : RAM16X1D
port map (DPO => fifo_00_data_out(1),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(1),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit1 : RAM16X1D
port map (DPO => fifo_01_data_out(1),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(1),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit2 : RAM16X1D
port map (DPO => fifo_00_data_out(2),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(2),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit2 : RAM16X1D
port map (DPO => fifo_01_data_out(2),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(2),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
fifo0_bit3 : RAM16X1D
port map (DPO => fifo_00_data_out(3),
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => dqs0_delayed_col0,
WE => fifo_00_wr_en );
fifo1_bit3 : RAM16X1D
port map (DPO => fifo_01_data_out(3),
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
D => ddr_dq_in(3),
DPRA0 => fifo_01_rd_addr(0),
DPRA1 => fifo_01_rd_addr(1),
DPRA2 => fifo_01_rd_addr(2),
DPRA3 => fifo_01_rd_addr(3),
WCLK => dqs0_delayed_col0_n,
WE => fifo_01_wr_en );
--- Nibble1 instantiation
fifo0_bit4 : RAM16X1D
port map (DPO => fifo_10_data_out(0),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit4 : RAM16X1D
port map (DPO => fifo_11_data_out(0),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
D => ddr_dq_in(4),
DPRA0 => fifo_11_rd_addr(0),
DPRA1 => fifo_11_rd_addr(1),
DPRA2 => fifo_11_rd_addr(2),
DPRA3 => fifo_11_rd_addr(3),
WCLK => dqs1_delayed_col0_n,
WE => fifo_11_wr_en );
fifo0_bit5 : RAM16X1D
port map (DPO => fifo_10_data_out(1),
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
D => ddr_dq_in(5),
DPRA0 => fifo_10_rd_addr(0),
DPRA1 => fifo_10_rd_addr(1),
DPRA2 => fifo_10_rd_addr(2),
DPRA3 => fifo_10_rd_addr(3),
WCLK => dqs1_delayed_col0,
WE => fifo_10_wr_en );
fifo1_bit5 : RAM16X1D
port map (DPO => fifo_11_data_out(1),
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
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