controller_iobs.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity controller_iobs is
port(
    clk0             : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
    ddr_rasb_cntrl   : in std_logic;
    ddr_casb_cntrl   : in std_logic;
    ddr_web_cntrl    : in std_logic;
    ddr_cke_cntrl    : in std_logic;
    ddr_csb_cntrl    : in std_logic;
    ddr_address_cntrl: in std_logic_vector(12 downto 0);
    ddr_ba_cntrl     : in std_logic_vector(1 downto 0);
    rst_dqs_div_int  : in std_logic;
    ddr_rasb         : out std_logic;
    ddr_casb         : out std_logic;
    ddr_web          : out std_logic;
    ddr_ba           : out std_logic_vector(1 downto 0);
    ddr_address      : out std_logic_vector(12 downto 0);
    ddr_cke          : out std_logic;
    ddr_csb          : out std_logic;
    rst_dqs_div      : out std_logic;
    rst_dqs_div_in   : in std_logic;
    rst_dqs_div_out  : out std_logic
   
);
end controller_iobs;


architecture arc_controller_iobs of controller_iobs is

attribute syn_keep : boolean;

component IBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;

component OBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;


component FD
   port(
      Q                              :  out   STD_LOGIC;
      D                              :  in    STD_LOGIC;
      C                              :  in    STD_LOGIC);
end component;

component OBUF
 port (
   O : out std_logic;
   I : in std_logic);
 end component;


--SYN_REMOVECOMMENT signal clk180     : std_logic;
signal GND        : std_logic;

 
--SYN_REMOVECOMMENT attribute syn_keep of clk180 : signal is true; 

begin

--SYN_REMOVECOMMENT clk180 <= not clk0;
GND <= '0';
  
---- ************************************* ----
----  Output buffers for control signals   ----
---- ************************************* ----


r0 : OBUF port map (
                     I => ddr_rasb_cntrl,
                     O => ddr_rasb);

r1 : OBUF port map (
                     I => ddr_casb_cntrl,
                     O => ddr_casb);
                     
r2 : OBUF port map (
                     I => ddr_web_cntrl,
                     O => ddr_web);

r3 : OBUF port map (
                     I => ddr_cke_cntrl,
                     O => ddr_cke);

r4 : OBUF port map (
                     I => ddr_csb_cntrl,
                     O => ddr_csb);

---- ************************************* ----
----  Output buffers for address signals   ----
---- ************************************* ----

r5 : OBUF port map (
                     I => ddr_address_cntrl(0),
                     O => ddr_address(0));

r6 : OBUF port map (
                     I => ddr_address_cntrl(1),
                     O => ddr_address(1));

r7 : OBUF port map (
                     I => ddr_address_cntrl(2),
                     O => ddr_address(2));

r8 : OBUF port map (
                     I => ddr_address_cntrl(3),
                     O => ddr_address(3));

r9 : OBUF port map (
                     I => ddr_address_cntrl(4),
                     O => ddr_address(4));

r10 : OBUF port map (
                     I => ddr_address_cntrl(5),
                     O => ddr_address(5));

r11 : OBUF port map (
                     I => ddr_address_cntrl(6),
                     O => ddr_address(6));

r12 : OBUF port map (
                     I => ddr_address_cntrl(7),
                     O => ddr_address(7));

r13 : OBUF port map (
                     I => ddr_address_cntrl(8),
                     O => ddr_address(8));

r14 : OBUF port map (
                     I => ddr_address_cntrl(9),
                     O => ddr_address(9));

r15 : OBUF port map (
                     I => ddr_address_cntrl(10),
                     O => ddr_address(10));

r16 : OBUF port map (
                     I => ddr_address_cntrl(11),
                     O => ddr_address(11));

r17 : OBUF port map (
                     I => ddr_address_cntrl(12),
                     O => ddr_address(12));



r18 : OBUF port map (
                     I => ddr_ba_cntrl(0),
                     O => ddr_ba(0));

r19 : OBUF port map (
                     I => ddr_ba_cntrl(1),
                     O => ddr_ba(1));



                        
rst_iob_inbuf  :  IBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_in,
                              O  => rst_dqs_div);
  

                            
rst_iob_outbuf  :  OBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_int,
                              O  => rst_dqs_div_out);


                             
end arc_controller_iobs;