📄 data_read_controller.vhd
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signal dqs17_delayed_col0 : std_logic;
-------------------- Changes Made On 28 JAN ----------------------------------
signal dqs0_delayed_col1 : std_logic;
signal dqs1_delayed_col1 : std_logic;
signal dqs2_delayed_col1 : std_logic;
signal dqs3_delayed_col1 : std_logic;
signal dqs4_delayed_col1 : std_logic;
signal dqs5_delayed_col1 : std_logic;
signal dqs6_delayed_col1 : std_logic;
signal dqs7_delayed_col1 : std_logic;
signal dqs8_delayed_col1 : std_logic;
signal dqs9_delayed_col1 : std_logic;
signal dqs10_delayed_col1 : std_logic;
signal dqs11_delayed_col1 : std_logic;
signal dqs12_delayed_col1 : std_logic;
signal dqs13_delayed_col1 : std_logic;
signal dqs14_delayed_col1 : std_logic;
signal dqs15_delayed_col1 : std_logic;
signal dqs16_delayed_col1 : std_logic;
signal dqs17_delayed_col1 : std_logic;
---------------------------------------------------------------------------------
-- dqsx_delayed_col0 negated signals
-- used for capturing negedge data into FIFO_*1
signal dqs0_delayed_col0_n : std_logic;
signal dqs1_delayed_col0_n : std_logic;
signal dqs2_delayed_col0_n : std_logic;
signal dqs3_delayed_col0_n : std_logic;
signal dqs4_delayed_col0_n : std_logic;
signal dqs5_delayed_col0_n : std_logic;
signal dqs6_delayed_col0_n : std_logic;
signal dqs7_delayed_col0_n : std_logic;
signal dqs8_delayed_col0_n : std_logic;
signal dqs9_delayed_col0_n : std_logic;
signal dqs10_delayed_col0_n : std_logic;
signal dqs11_delayed_col0_n : std_logic;
signal dqs12_delayed_col0_n : std_logic;
signal dqs13_delayed_col0_n : std_logic;
signal dqs14_delayed_col0_n : std_logic;
signal dqs15_delayed_col0_n : std_logic;
signal dqs16_delayed_col0_n : std_logic;
signal dqs17_delayed_col0_n : std_logic;
-- Directive for synthesis
attribute syn_keep of dqs0_delayed_col0_n : signal is true;
attribute syn_keep of dqs1_delayed_col0_n : signal is true;
attribute syn_keep of dqs2_delayed_col0_n : signal is true;
attribute syn_keep of dqs3_delayed_col0_n : signal is true;
attribute syn_keep of dqs4_delayed_col0_n : signal is true;
attribute syn_keep of dqs5_delayed_col0_n : signal is true;
attribute syn_keep of dqs6_delayed_col0_n : signal is true;
attribute syn_keep of dqs7_delayed_col0_n : signal is true;
attribute syn_keep of dqs8_delayed_col0_n : signal is true;
attribute syn_keep of dqs9_delayed_col0_n : signal is true;
attribute syn_keep of dqs10_delayed_col0_n : signal is true;
attribute syn_keep of dqs11_delayed_col0_n : signal is true;
attribute syn_keep of dqs12_delayed_col0_n : signal is true;
attribute syn_keep of dqs13_delayed_col0_n : signal is true;
attribute syn_keep of dqs14_delayed_col0_n : signal is true;
attribute syn_keep of dqs15_delayed_col0_n : signal is true;
attribute syn_keep of dqs16_delayed_col0_n : signal is true;
attribute syn_keep of dqs17_delayed_col0_n : signal is true;
signal dqs0_delayed_col1_n : std_logic;
signal dqs1_delayed_col1_n : std_logic;
signal dqs2_delayed_col1_n : std_logic;
signal dqs3_delayed_col1_n : std_logic;
signal dqs4_delayed_col1_n : std_logic;
signal dqs5_delayed_col1_n : std_logic;
signal dqs6_delayed_col1_n : std_logic;
signal dqs7_delayed_col1_n : std_logic;
signal dqs8_delayed_col1_n : std_logic;
signal dqs9_delayed_col1_n : std_logic;
signal dqs10_delayed_col1_n : std_logic;
signal dqs11_delayed_col1_n : std_logic;
signal dqs12_delayed_col1_n : std_logic;
signal dqs13_delayed_col1_n : std_logic;
signal dqs14_delayed_col1_n : std_logic;
signal dqs15_delayed_col1_n : std_logic;
signal dqs16_delayed_col1_n : std_logic;
signal dqs17_delayed_col1_n : std_logic;
-- Directive for synthesis
attribute syn_keep of dqs0_delayed_col1_n : signal is true;
attribute syn_keep of dqs1_delayed_col1_n : signal is true;
attribute syn_keep of dqs2_delayed_col1_n : signal is true;
attribute syn_keep of dqs3_delayed_col1_n : signal is true;
attribute syn_keep of dqs4_delayed_col1_n : signal is true;
attribute syn_keep of dqs5_delayed_col1_n : signal is true;
attribute syn_keep of dqs6_delayed_col1_n : signal is true;
attribute syn_keep of dqs7_delayed_col1_n : signal is true;
attribute syn_keep of dqs8_delayed_col1_n : signal is true;
attribute syn_keep of dqs9_delayed_col1_n : signal is true;
attribute syn_keep of dqs10_delayed_col1_n : signal is true;
attribute syn_keep of dqs11_delayed_col1_n : signal is true;
attribute syn_keep of dqs12_delayed_col1_n : signal is true;
attribute syn_keep of dqs13_delayed_col1_n : signal is true;
attribute syn_keep of dqs14_delayed_col1_n : signal is true;
attribute syn_keep of dqs15_delayed_col1_n : signal is true;
attribute syn_keep of dqs16_delayed_col1_n : signal is true;
attribute syn_keep of dqs17_delayed_col1_n : signal is true;
-- FIFO WRITE ENABLE SIGNALS
signal fifo_00_wr_en : std_logic;
signal fifo_10_wr_en : std_logic;
signal fifo_20_wr_en : std_logic;
signal fifo_30_wr_en : std_logic;
signal fifo_40_wr_en : std_logic;
signal fifo_50_wr_en : std_logic;
signal fifo_60_wr_en : std_logic;
signal fifo_70_wr_en : std_logic;
signal fifo_80_wr_en : std_logic;
signal fifo_90_wr_en : std_logic;
signal fifo_100_wr_en : std_logic;
signal fifo_110_wr_en : std_logic;
signal fifo_120_wr_en : std_logic;
signal fifo_130_wr_en : std_logic;
signal fifo_140_wr_en : std_logic;
signal fifo_150_wr_en : std_logic;
signal fifo_160_wr_en : std_logic;
signal fifo_170_wr_en : std_logic;
signal fifo_01_wr_en : std_logic;
signal fifo_11_wr_en : std_logic;
signal fifo_21_wr_en : std_logic;
signal fifo_31_wr_en : std_logic;
signal fifo_41_wr_en : std_logic;
signal fifo_51_wr_en : std_logic;
signal fifo_61_wr_en : std_logic;
signal fifo_71_wr_en : std_logic;
signal fifo_81_wr_en : std_logic;
signal fifo_91_wr_en : std_logic;
signal fifo_101_wr_en : std_logic;
signal fifo_111_wr_en : std_logic;
signal fifo_121_wr_en : std_logic;
signal fifo_131_wr_en : std_logic;
signal fifo_141_wr_en : std_logic;
signal fifo_151_wr_en : std_logic;
signal fifo_161_wr_en : std_logic;
signal fifo_171_wr_en : std_logic;
-- FIFO_WR_POINTER Delayed signals in clk90 domain
signal fifo_00_wr_addr_d : std_logic_vector(3 downto 0);
signal fifo_00_wr_addr_2d : std_logic_vector(3 downto 0);
signal fifo_01_wr_addr_d : std_logic_vector(3 downto 0);
signal fifo_01_wr_addr_2d : std_logic_vector(3 downto 0);
-- DDR_DQ_IN signals from DDR_DQ Input buffer
signal ddr_dq_in : std_logic_vector(143 downto 0);
signal write_data270_1 : std_logic_vector(143 downto 0);
signal write_data270_2 : std_logic_vector(143 downto 0);
signal rst_dqs_div1 : std_logic;
signal rst_dqs_div2 : std_logic;
signal rst_dqs_delay_0_n : std_logic;
signal rst_dqs_delay_1_n : std_logic;
signal rst_dqs_delay_2_n : std_logic;
signal rst_dqs_delay_3_n : std_logic;
signal rst_dqs_delay_4_n : std_logic;
signal rst_dqs_delay_5_n : std_logic;
signal rst_dqs_delay_6_n : std_logic;
signal rst_dqs_delay_7_n : std_logic;
signal rst_dqs_delay_8_n : std_logic;
signal rst_dqs_delay_9_n : std_logic;
signal rst_dqs_delay_10_n : std_logic;
signal rst_dqs_delay_11_n : std_logic;
signal rst_dqs_delay_12_n : std_logic;
signal rst_dqs_delay_13_n : std_logic;
signal rst_dqs_delay_14_n : std_logic;
signal rst_dqs_delay_15_n : std_logic;
signal rst_dqs_delay_16_n : std_logic;
signal rst_dqs_delay_17_n : std_logic;
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
begin
fifo_00_wr_addr_val <= fifo_00_wr_addr;
fifo_01_wr_addr_val <= fifo_01_wr_addr;
fifo_10_wr_addr_val <= fifo_10_wr_addr;
fifo_11_wr_addr_val <= fifo_11_wr_addr;
fifo_20_wr_addr_val <= fifo_20_wr_addr;
fifo_21_wr_addr_val <= fifo_21_wr_addr;
fifo_30_wr_addr_val <= fifo_30_wr_addr;
fifo_31_wr_addr_val <= fifo_31_wr_addr;
fifo_40_wr_addr_val <= fifo_40_wr_addr;
fifo_41_wr_addr_val <= fifo_41_wr_addr;
fifo_50_wr_addr_val <= fifo_50_wr_addr;
fifo_51_wr_addr_val <= fifo_51_wr_addr;
fifo_60_wr_addr_val <= fifo_60_wr_addr;
fifo_61_wr_addr_val <= fifo_61_wr_addr;
fifo_70_wr_addr_val <= fifo_70_wr_addr;
fifo_71_wr_addr_val <= fifo_71_wr_addr;
fifo_80_wr_addr_val <= fifo_80_wr_addr;
fifo_81_wr_addr_val <= fifo_81_wr_addr;
fifo_90_wr_addr_val <= fifo_90_wr_addr;
fifo_91_wr_addr_val <= fifo_91_wr_addr;
fifo_100_wr_addr_val <= fifo_100_wr_addr;
fifo_101_wr_addr_val <= fifo_101_wr_addr;
fifo_110_wr_addr_val <= fifo_110_wr_addr;
fifo_111_wr_addr_val <= fifo_111_wr_addr;
fifo_120_wr_addr_val <= fifo_120_wr_addr;
fifo_121_wr_addr_val <= fifo_121_wr_addr;
fifo_130_wr_addr_val <= fifo_130_wr_addr;
fifo_131_wr_addr_val <= fifo_131_wr_addr;
fifo_140_wr_addr_val <= fifo_140_wr_addr;
fifo_141_wr_addr_val <= fifo_141_wr_addr;
fifo_150_wr_addr_val <= fifo_150_wr_addr;
fifo_151_wr_addr_val <= fifo_151_wr_addr;
fifo_160_wr_addr_val <= fifo_160_wr_addr;
fifo_161_wr_addr_val <= fifo_161_wr_addr;
fifo_170_wr_addr_val <= fifo_170_wr_addr;
fifo_171_wr_addr_val <= fifo_171_wr_addr;
fifo_00_wr_en_val <= fifo_00_wr_en;
fifo_10_wr_en_val <= fifo_10_wr_en;
fifo_20_wr_en_val <= fifo_20_wr_en;
fifo_30_wr_en_val <= fifo_30_wr_en;
fifo_40_wr_en_val <= fifo_40_wr_en;
fifo_50_wr_en_val <= fifo_50_wr_en;
fifo_60_wr_en_val <= fifo_60_wr_en;
fifo_70_wr_en_val <= fifo_70_wr_en;
fifo_80_wr_en_val <= fifo_80_wr_en;
fifo_90_wr_en_val <= fifo_90_wr_en;
fifo_100_wr_en_val <= fifo_100_wr_en;
fifo_110_wr_en_val <= fifo_110_wr_en;
fifo_120_wr_en_val <= fifo_120_wr_en;
fifo_130_wr_en_val <= fifo_130_wr_en;
fifo_140_wr_en_val <= fifo_140_wr_en;
fifo_150_wr_en_val <= fifo_150_wr_en;
fifo_160_wr_en_val <= fifo_160_wr_en;
fifo_170_wr_en_val <= fifo_170_wr_en;
fifo_01_wr_en_val <= fifo_01_wr_en;
fifo_11_wr_en_val <= fifo_11_wr_en;
fifo_21_wr_en_val <= fifo_21_wr_en;
fifo_31_wr_en_val <= fifo_31_wr_en;
fifo_41_wr_en_val <= fifo_41_wr_en;
fifo_51_wr_en_val <= fifo_51_wr_en;
fifo_61_wr_en_val <= fifo_61_wr_en;
fifo_71_wr_en_val <= fifo_71_wr_en;
fifo_81_wr_en_val <= fifo_81_wr_en;
fifo_91_wr_en_val <= fifo_91_wr_en;
fifo_101_wr_en_val <= fifo_101_wr_en;
fifo_111_wr_en_val <= fifo_111_wr_en;
fifo_121_wr_en_val <= fifo_121_wr_en;
fifo_131_wr_en_val <= fifo_131_wr_en;
fifo_141_wr_en_val <= fifo_141_wr_en;
fifo_151_wr_en_val <= fifo_151_wr_en;
fifo_161_wr_en_val <= fifo_161_wr_en;
fifo_171_wr_en_val <= fifo_171_wr_en;
dqs0_delayed_col1_val <= dqs0_delayed_col1;
dqs1_delayed_col1_val <= dqs1_delayed_col1;
dqs2_delayed_col1_val <= dqs2_delayed_col1;
dqs3_delayed_col1_val <= dqs3_delayed_col1;
dqs4_delayed_col1_val <= dqs4_delayed_col1;
dqs5_delayed_col1_val <= dqs5_delayed_col1;
dqs6_delayed_col1_val <= dqs6_delayed_col1;
dqs7_delayed_col1_val <= dqs7_delayed_col1;
dqs8_delayed_col1_val <= dqs8_delayed_col1;
dqs9_delayed_col1_val <= dqs9_delayed_col1;
dqs10_delayed_col1_val <= dqs10_delayed_col1;
dqs11_delayed_col1_val <= dqs11_delayed_col1;
dqs12_delayed_col1_val <= dqs12_delayed_col1;
dqs13_delayed_col1_val <= dqs13_delayed_col1;
dqs14_delayed_col1_val <= dqs14_delayed_col1;
dqs15_delayed_col1_val <= dqs15_delayed_col1;
dqs16_delayed_col1_val <= dqs16_delayed_col1;
dqs17_delayed_col1_val <= dqs17_delayed_col1;
dqs0_delayed_col0_n_val <= dqs0_delayed_col0_n;
dqs1_delayed_col0_n_val <= dqs1_delayed_col0_n;
dqs2_delayed_col0_n_val <= dqs2_delayed_col0_n;
dqs3_delayed_col0_n_val <= dqs3_delayed_col0_n;
dqs4_delayed_col0_n_val <= dqs4_delayed_col0_n;
dqs5_delayed_col0_n_val <= dqs5_delayed_col0_n;
dqs6_delayed_col0_n_val <= dqs6_delayed_col0_n;
dqs7_delayed_col0_n_val <= dqs7_delayed_col0_n;
dqs8_delayed_col0_n_val <= dqs8_delayed_col0_n;
dqs9_delayed_col0_n_val <= dqs9_delayed_col0_n;
dqs10_delayed_col0_n_val <= dqs10_delayed_col0_n;
dqs11_delayed_col0_n_val <= dqs11_delayed_col0_n;
dqs12_delayed_col0_n_val <= dqs12_delayed_col0_n;
dqs13_delayed_col0_n_val <= dqs13_delayed_col0_n;
dqs14_delayed_col0_n_val <= dqs14_delayed_col0_n;
dqs15_delayed_col0_n_val <= dqs15_delayed_col0_n;
dqs16_delayed_col0_n_val <= dqs16_delayed_col0_n;
dqs17_delayed_col0_n_val <= dqs17_delayed_col0_n;
fifo0_rd_addr_val <= fifo0_rd_addr;
fifo1_rd_addr_val <= fifo1_rd_addr;
-- data_valid signal is derived from fifo_00 and fifo_01 empty signals only
-- FIFO WRITE POINTER DELAYED SIGNALS
-- To avoid meta-stability due to the domain crossing from ddr_dqs to clk90
process (clk90)
begin
if (rising_edge(clk90)) then
if (reset90_r = '1') then
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