generic_ucf.txt

XILINX memory interface generator. XILINX的外部存储器接口。

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## FIFO read and write address maxdelay contraint
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NET "%sQDR_Interface_B/Read_data_path/fifo_*_wr_addr*"  MAXDELAY = 3000ps;
NET "%sQDR_Interface_B/Read_data_path/fifo_*_rd_addr*"  MAXDELAY = 3000ps;
 
 

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# Calibration Circuit Constraints
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NET "%sQDR_Interface_B/cal_inst/clkDiv2" MAXDELAY = 600 ps;
NET "%sQDR_Interface_B/cal_inst/phClkDiv2" MAXDELAY = 600 ps;

NET "%sQDR_Interface_B/cal_inst/suClkDiv2" MAXDELAY = 600ps;
NET "%sQDR_Interface_B/cal_inst/suPhClkDiv2" MAXDELAY = 700ps;

NET "%sQDR_Interface_B/QDR_R_n_ext_stage1" MAXDELAY = 1200ps;

NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay1" KEEP;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay2" KEEP;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay3" KEEP;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay4" KEEP;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay5" KEEP;

NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay1" S;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay2" S;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay3" S;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay4" S;
NET "%sQDR_Interface_B/cal_inst/ckt_to_cal/delay5" S;

NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(0)" S;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(1)" S;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(2)" S;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(3)" S;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(4)" S;

NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(0)" KEEP;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(1)" KEEP;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(2)" KEEP;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(3)" KEEP;
NET "%sQDR_Interface_B/cal_inst/cal_ctl0/selTap(4)" KEEP;



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