2vp30ff1152.txt

XILINX memory interface generator. XILINX的外部存储器接口。

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# DCM, MACRO and BUFG  Constraints
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INST "%sQDR_Interface_clocks/INST_DCM_TOMEMORY" LOC="DCM_X3Y0";

############################################################################
# Calibration Circuit Constraints
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INST "%sQDR_Interface_B/cal_inst/cal_dcm" LOC="DCM_X2Y0";

INST "%sQDR_Interface_B/cal_inst" AREA_GROUP=gp1;
AREA_GROUP "gp1" RANGE = SLICE_X52Y0:SLICE_X75Y11;

INST "%sQDR_Interface_B/cal_inst/cal_clkd2" LOC = SLICE_X72Y0;
INST "%sQDR_Interface_B/cal_inst/cal_phClkd2" LOC = SLICE_X72Y3;

INST "%sQDR_Interface_B/cal_inst/hxSampReg0" LOC = SLICE_X74Y0;

INST "%sQDR_Interface_B/cal_inst/cal_suClkd2" LOC = SLICE_X72Y4;
INST "%sQDR_Interface_B/cal_inst/cal_suPhClkd2" LOC = SLICE_X74Y5;
INST "%sQDR_Interface_B/cal_inst/phSampReg0" LOC = SLICE_X74Y4;

#############################################################
# LUT Location Constraints for cq_delay Circuit
#############################################################

INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/one" LOC = SLICE_X74Y2;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/one" BEL = F;

INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/two" LOC = SLICE_X74Y3;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/two" BEL = F;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/three" LOC = SLICE_X74Y3;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/three" BEL = G;

INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/four" LOC = SLICE_X75Y2;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/four" BEL = F;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/five" LOC = SLICE_X75Y2;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/five" BEL = G;

INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/six" LOC = SLICE_X75Y3;
INST "%sQDR_Interface_B/cal_inst/ckt_to_cal/six" BEL = G;