qdr2_test.edf

XILINX memory interface generator. XILINX的外部存储器接口。

(edif (rename qdr2_test "QDR_LC_TOP")
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2004 9 28 17 13 38)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "7.3.3, Build 039R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell OBUF_LVDCI_25 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF_HSTL_II_18 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IBUF_LVCMOS25 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IBUF_HSTL_I_DCI_18 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IBUF_HSTL_II_18 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IBUFGDS_LVDS_25 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
           (port IB (direction INPUT))
         )
       )
    )
    (cell FDDRRSE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port C0 (direction INPUT))
           (port C1 (direction INPUT))
           (port CE (direction INPUT))
           (port D0 (direction INPUT))
           (port D1 (direction INPUT))
           (port R (direction INPUT))
           (port S (direction INPUT))
         )
       )
    )
    (cell DCM (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port (array (rename status "STATUS[7:0]") 8) (direction OUTPUT))
           (port CLKFB (direction INPUT))
           (port CLKIN (direction INPUT))
           (port DSSEN (direction INPUT))
           (port PSCLK (direction INPUT))
           (port PSEN (direction INPUT))
           (port PSINCDEC (direction INPUT))
           (port RST (direction INPUT))
           (port CLK0 (direction OUTPUT))
           (port CLK90 (direction OUTPUT))
           (port CLK180 (direction OUTPUT))
           (port CLK270 (direction OUTPUT))
           (port CLK2X (direction OUTPUT))
           (port CLK2X180 (direction OUTPUT))
           (port CLKDV (direction OUTPUT))
           (port CLKFX (direction OUTPUT))
           (port CLKFX180 (direction OUTPUT))
           (port LOCKED (direction OUTPUT))
           (port PSDONE (direction OUTPUT))
         )
       )
    )
    (cell RAM16X1D (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DPO (direction OUTPUT))
           (port SPO (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
           (port A3 (direction INPUT))
           (port D (direction INPUT))
           (port DPRA0 (direction INPUT))
           (port DPRA1 (direction INPUT))
           (port DPRA2 (direction INPUT))
           (port DPRA3 (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT4_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell XORCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port LI (direction INPUT))
           (port CI (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXCY_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell BUFG (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDS (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port S (direction INPUT))
         )
       )
    )
    (cell FDR (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port R (direction INPUT))
         )
       )
    )
    (cell FDRS_1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port R (direction INPUT))
           (port S (direction INPUT))
         )
       )
    )
    (cell FDSE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port S (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDRE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port R (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDRSE_1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port R (direction INPUT))
           (port S (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDRSE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port R (direction INPUT))
           (port S (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FD (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))