qdr2_qbit_cq_bar.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
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`timescale 1 ns/1 ps

module qdr2_qbit_cq_bar( reset,    
                         cq,       
                         cq1,      
                         qdr2_q,   
                         CE_R_FB0,
                         CE_R_FB1,
                         CE_R_FB2,
                         CE_R_FB3,
                         fbit_0,   
                         fbit_1,   
                         fbit_2,   
                         fbit_3);   

input  reset; 
input  cq; 
input  cq1; 
input  qdr2_q; 
input  CE_R_FB0; 
input  CE_R_FB1;
input  CE_R_FB2;
input  CE_R_FB3;
output fbit_0;
output fbit_1;
output fbit_2;
output fbit_3;

wire              q;
wire [3:0]        fbit;
wire              async_clr;
wire              cqn;      
wire              cq1n;
//wire              cq_div2n; 
//wire              cq_div1n; 
wire              CE_R_FB0;
wire              CE_R_FB1;
wire              CE_R_FB2;
wire              CE_R_FB3;

assign async_clr = reset;   
assign cqn      = ~cq;
assign cq1n     = ~cq1;
//assign cq_div2n = ~cq_div_2;
//assign cq_div1n = ~cq_div_1;
assign fbit_0   = fbit[0];
assign fbit_1   = fbit[1];
assign fbit_2   = fbit[2];
assign fbit_3   = fbit[3];

// Read data from memory is first registered in CLB ff using delayed strobe from memory
// A data bit from data words 0, 1, 2, and 3

 FDCE fbit0 (.Q(fbit[0]),
             .C(cq1),
             .CE(CE_R_FB0),
             .CLR(async_clr),
             .D(q));
           
 FDCE fbit1 (.Q(fbit[1]),    
             .C(cqn),                        
             .CE(CE_R_FB1),                  
             .CLR(async_clr),                
             .D(q));                                                                      
           
 FDCE fbit2 (.Q(fbit[2]),    
             .C(cq1),                                     
             .CE(CE_R_FB2),                               
             .CLR(async_clr),                             
             .D(q));                                      
                                                      
 FDCE fbit3 (.Q(fbit[3]),    
             .C(cqn),                                          
             .CE(CE_R_FB3),                                    
             .CLR(async_clr),                                  
             .D(q));
             
// Generation of the synchronous CE for the data capture FD.
/* FD FD_R_n_0 (.Q(CE_R_FB0),
             .C(cq1n),
             .D(R_n_int_w0));
           
 FD FD_R_n_1 (.Q(CE_R_FB1),    
             .C(cq),                                   
             .D(CE_R_FB0));                                                                      
           
 FD FD_R_n_2 (.Q(CE_R_FB2),    
             .C(cq1n),                                                                 
             .D(CE_R_FB0));                                      
                                                      
 FD FD_R_n_3 (.Q(CE_R_FB3),    
             .C(cq),                                                                          
             .D(CE_R_FB1));   */                                             
 
v2p_qdr2_input_buffer v2p_qdr2_iob0 ( .qdr2_in(qdr2_q), .read_data_in(q) ); 

endmodule