cal_top.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
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//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
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// Top level for calibration circuit.
//  - instantiate DCM, calib control, and ckt to calibrate

`timescale 1ns/100ps

`define noMuxF5 1'b1


module cal_top(
	       clk,
	       clk0,
	       clk0dcmlock,
	       reset,
	       okToSelTap,
	       tapForDqs
               );
               
   input          clk;
   input          clk0;
   input 	  clk0dcmlock;
   input 	  reset;
   input 	  okToSelTap;
   
   output [4:0]   tapForDqs;
   
   wire 	  reset;
   wire 	  phShftClk;
   wire 	  phShftClkDcm;
   wire 	  psInc;
   wire 	  psEn;
   wire 	  dcmlocked;
   wire 	  psDone;
   wire 	  hexClk;
   wire 	  clkDiv2/* synthesis syn_keep = 1 */;
   wire 	  phClkDiv2/* synthesis syn_keep = 1 */;
   wire       suClkDiv2/* synthesis syn_keep = 1 */;
   wire       suPhClkDiv2/* synthesis syn_keep = 1 */;


   wire [4:0] 	  selTap;
   wire [4:0] 	  tapForDqs;
   wire [3:0] 	  state;
   wire 	  locReset;
   wire 	  hxSamp1;
   
   wire 	  clk0;//signals added for additional dcm

   reg 	  fpga_rst;//
   
   
   // synopsys translate_off
   // Attributes for RTL simulation
   defparam cal_dcm.CLKOUT_PHASE_SHIFT = "VARIABLE" ;
   //defparam cal_dcm.PHASE_SHIFT = 0 ;
   // defparam cal_dcm.CLKDV_DIVIDE = 4.0 ;
   defparam cal_dcm.DLL_FREQUENCY_MODE = "LOW" ;
   // defparam cal_dcm.CLKIN_DIVIDE_BY_2 = "FALSE" ;
   // synopsys translate_on
   
   DCM cal_dcm (
		.CLKIN(clk),                     // input clock
		.CLKFB(phShftClk),               // output clock
		.DSSEN(1'b0),
		.PSINCDEC(psInc),
		.PSEN(psEn),
		.PSCLK(clk0),
		.RST(reset), 
		.CLK0(phShftClkDcm),
		.CLK90(),
		.CLK180(),
		.CLK270(),
		.CLK2X(),
		.CLK2X180(),
		.CLKDV(),
		.CLKFX(),
		.CLKFX180(),
		.LOCKED(dcmlocked),
		.PSDONE(psDone),
		.STATUS())

   
   /*synthesis DUTY_CYCLE_CORRECTION = "TRUE"
    CLKOUT_PHASE_SHIFT = "VARIABLE" 
    PHASE_SHIFT = 0
    DLL_FREQUENCY_MODE = "LOW" */

   // Synplicity attributes
   ;

always @ (posedge clk0)
begin
  fpga_rst <= ~(reset & dcmlocked & clk0dcmlock);
end

   
   BUFG phclk_bufg (.I(phShftClkDcm),
		    .O(phShftClk)
		    );
   
   cal_ctl cal_ctl0(
		    .clk (clk0),
		    .psDone(psDone),
		    .reset(fpga_rst),//changed from reset
		    .okToSelTap(okToSelTap),
		    .locReset(locReset),
		    .hxSamp1(hxSamp1),
		    .phSamp1(phSamp1),
		    .selTap(selTap[4:0]),
		    .psEn(psEn),
		    .psInc(psInc),
		    .dcmlocked(dcmlocked),
		    .tapForDqs(tapForDqs[4:0])
		    );

   wire     divRst;
   assign   divRst = ~(dcmlocked && clk0dcmlock);
   
   
   cal_div2 cal_clkd2(
		      .reset (divRst),
		      .iclk(clk0),
		      .oclk(clkDiv2)
		      )/* synthesis syn_noprune=1 */;


   cal_div2 cal_phClkd2(
			.reset (divRst),
			.iclk(phShftClk),
			.oclk(phClkDiv2)
			)/* synthesis syn_noprune=1 */;

   
   
   cal_reg hxSampReg0(
		      .reset (fpga_rst), //changed from reset
		      .clk(hexClk),
		      .dInp(clkDiv2),
		      .iReg(hxSamp0),
		      .dReg(hxSamp1)
		      )/* synthesis syn_noprune=1 */;


   cal_div2 cal_suClkd2(
			.reset (divRst),
			.iclk(clk0),
			.oclk(suClkDiv2)
			)/* synthesis syn_noprune=1 */;


   
   cal_div2 cal_suPhClkd2(
			  .reset (divRst),
			  .iclk(phShftClk),
			  .oclk(suPhClkDiv2)
			  )/* synthesis syn_noprune=1 */;
   
      
   cal_reg phSampReg0(
		      .reset (fpga_rst), //changed from reset
		      .clk(suPhClkDiv2),
		      .dInp(suClkDiv2),
		      .iReg(phSamp0),
		      .dReg(phSamp1)
		      )/* synthesis syn_noprune=1 */;

   

     
   cq_delay  ckt_to_cal 
     //cq_dly_sim ckt_to_cal
     (
      .clk_in (phClkDiv2),
      .sel_in(selTap[4:0]),
      .clk_out(hexClk)
      )/* synthesis syn_noprune=1 */;


  
endmodule // cal_top