qdr2_clocks.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//** 
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
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// This module is the top level architecture for the memory interface design.
// The signals connections are describled in the application note. 
// The naming convention is as follows:
// - user side: USER_INSTNAME
// - memory side: QDR_INSTNAME

`timescale 1 ns/1 ps

module qdr2_clocks ( USER_CLK, 
                     USER_CLK_N,
                     RESET, 
		     CLK_BUF,
                     GCLK0,
                     GCLK90,
                     GCLK180,
                     GCLK270,
		     CLKDIV2,
		     LOCKED_DCM);

        input USER_CLK;
        input USER_CLK_N;
        input RESET;

	output CLK_BUF;
        output GCLK0;
        output GCLK90;
        output GCLK180;
        output GCLK270;
        output CLKDIV2;

	output LOCKED_DCM;
	
	wire LOCKED_DCM_SEC;
	wire LOCKED_DCM_PRI;           
	wire GND;                                                        
	wire HIGH;

	wire CLK_BUF;
	wire CLK0E_BUF; 
	wire CLK90E_BUF;  
	wire CLK180E_BUF;
	wire CLK270E_BUF;
	wire CLK_DV_BUF;                                   

	wire CLK0E;                                                                                                      
	wire CLK90E;
	wire CLK270E;                                                                                                    
	wire CLK180E;      

	
// Signals assigment                                                        
        
        assign GND = 1'b0;
        assign GCLK0 = CLK0E;
        assign GCLK90 = CLK90E;
        assign GCLK180 = CLK180E;
        assign GCLK270 = CLK270E;
 

	assign LOCKED_DCM = ( LOCKED_DCM_PRI);
// Clock buffer                                                                                                            
IBUFGDS_LVDS_25 IBUFG_GENE (.O(CLK_BUF), .I(USER_CLK), .IB(USER_CLK_N));

// DCM instanciation for the memory controller                                                                                           
DCM INST_DCM_TOMEMORY (.CLK0(CLK0E_BUF),
                       .CLK90(CLK90E_BUF),
                       .CLK180(CLK180E_BUF), 
                       .CLK270(CLK270E_BUF),
                       .CLK2X(),                                         
                       .CLK2X180(),
                       .CLKDV(), 
                       .CLKFX(),                                         
                       .CLKFX180(),
                       .LOCKED(LOCKED_DCM_PRI),
                       .PSDONE(),
                       .STATUS(),
                       .CLKFB(CLK0E),
                       .CLKIN(CLK_BUF), //CLK external generated by a frequency generator, at 200 MHz
                       .DSSEN(GND),  
                       .PSCLK(GND),
                       .PSEN(GND), 
                       .PSINCDEC(GND), 
                       .RST(RESET)                      
                       );           
                       
// The test design requires CLK0 /2. The number of direct clock interconnect per DCM is 4,
// and CLK0 through 270 are using these clocks. 
// An addition DCM is used to generate CLK0/2 in order to maintain low clock tree skew.                                                                                          
/*DCM INST_DCM_DIV2TEST (.CLK0(),
                       .CLK90(),
                       .CLK180(), 
                       .CLK270(),
                       .CLK2X(),                                         
                       .CLK2X180(),
                       .CLKDV(CLK_DV_BUF), 
                       .CLKFX(),                                         
                       .CLKFX180(),
                       .LOCKED(LOCKED_DCM_SEC),
                       .PSDONE(),
                       .STATUS(),
                       .CLKFB(CLK0E),
                       .CLKIN(CLK_BUF), //CLK external generated by a frequency generator, at 200 MHz
                       .DSSEN(GND),  
                       .PSCLK(GND),
                       .PSEN(GND), 
                       .PSINCDEC(GND), 
                       .RST(RESET)                      
                       );           
*/                       
 // BUFG instanciation                                                                                                                                                 


BUFG BUFG_Sec_0	(.O(CLK0E), .I(CLK0E_BUF));                           
BUFG BUFG_Sec_90 (.O(CLK90E), .I(CLK90E_BUF));       
BUFG BUFG_Sec_180 (.O(CLK180E), .I(CLK180E_BUF));
BUFG BUFG_Sec_270 (.O(CLK270E), .I(CLK270E_BUF));
BUFG BUFG_CLKDIV2 (.O(CLKDIV2), .I(CLK_DV_BUF));


endmodule