qdr2_transfer_done.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//**
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
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`timescale 1 ns/1 ps


module qdr2_transfer_done (clk0,          
                           clk90,         
                           clk180,        
                           clk270,        
                           reset,         
                           reset90,       
                           reset180,      
                           reset270,      
                           cq_div,        
                           transfer_done0,
                           transfer_done1,
                           transfer_done2,
                           transfer_done3);

input  clk0;            
input  clk90;             
input  clk180;            
input  clk270;            
input  reset;             
input  reset90;           
input  reset180;          
input  reset270;          
input  cq_div;            
output transfer_done0;    
output transfer_done1;    
output transfer_done2;    
output transfer_done3;   
                         
wire [3:0] transfer_done_int;
wire transfer_done0_clk0;
wire transfer_done0_clk90;
wire transfer_done0_clk180;
wire transfer_done0_clk270;
wire transfer_done1_clk90;
wire transfer_done1_clk270;
wire transfer_done2_clk90;
wire transfer_done2_clk270;
wire transfer_done3_clk90;
wire transfer_done3_clk270;
wire sync_rst_xdone0_ck0;
wire sync_rst_xdone0_ck180;
wire sync_rst_clk90;
wire sync_rst_clk270;

assign sync_rst_xdone0_ck0 = (reset || transfer_done0_clk0); 
assign sync_rst_xdone0_ck180 = (reset180 || transfer_done0_clk180);

assign transfer_done0 = transfer_done_int[0];
assign transfer_done1 = transfer_done_int[1];
assign transfer_done2 = transfer_done_int[2];
assign transfer_done3 = transfer_done_int[3];

LUT2 xdone0 ( .O (transfer_done_int[0]), .I0(transfer_done0_clk90), .I1(transfer_done0_clk270)) /* synthesis xc_props="INIT=e" */;
defparam xdone0.INIT = 4'he;
LUT2 xdone1 ( .O (transfer_done_int[1]), .I0(transfer_done1_clk90), .I1(transfer_done1_clk270)) /* synthesis xc_props="INIT=e" */; 
defparam xdone1.INIT = 4'he;
LUT2 xdone2 ( .O (transfer_done_int[2]), .I0(transfer_done2_clk90), .I1(transfer_done2_clk270)) /* synthesis xc_props="INIT=e" */; 
defparam xdone2.INIT = 4'he;
LUT2 xdone3 ( .O (transfer_done_int[3]), .I0(transfer_done3_clk90), .I1(transfer_done3_clk270)) /* synthesis xc_props="INIT=e" */; 
defparam xdone3.INIT = 4'he;
FDR xdone0_clk0 ( .Q(transfer_done0_clk0), .C(clk0), .R(sync_rst_xdone0_ck0), .D(cq_div));
FDR xdone0_clk90 ( .Q(transfer_done0_clk90), .C(clk90), .R(sync_rst_clk90), .D(transfer_done0_clk0));
FDR xdone0_clk180 ( .Q(transfer_done0_clk180), .C(clk180), .R(sync_rst_xdone0_ck180), .D(cq_div));
FDR xdone0_clk270 ( .Q(transfer_done0_clk270), .C(clk270), .R(sync_rst_clk270), .D(transfer_done0_clk180));  
                              
LUT3 xdone0_rst90 ( .O (sync_rst_clk90), .I0(reset90), .I1(transfer_done0_clk270), .I2(transfer_done0_clk90)) /* synthesis xc_props="INIT=fe" */;    
defparam xdone0_rst90.INIT = 8'hfe;
LUT3 xdone0_rst270 ( .O (sync_rst_clk270), .I0(reset270), .I1(transfer_done0_clk270), .I2(transfer_done0_clk90)) /* synthesis xc_props="INIT=fe" */;                                                                 
defparam xdone0_rst270.INIT = 8'hfe;
                            
FD xdone1_clk90 ( .Q(transfer_done1_clk90), .C(clk90), .D(transfer_done0_clk270));
FD xdone1_clk270 ( .Q(transfer_done1_clk270), .C(clk270), .D(transfer_done0_clk90));
FD xdone2_clk90 ( .Q(transfer_done2_clk90), .C(clk90), .D(transfer_done1_clk270));
FD xdone2_clk270 ( .Q(transfer_done2_clk270), .C(clk270), .D(transfer_done1_clk90));
FD xdone3_clk90 ( .Q(transfer_done3_clk90), .C(clk90), .D(transfer_done2_clk270));
FD xdone3_clk270 ( .Q(transfer_done3_clk270), .C(clk270), .D(transfer_done2_clk90));                                                          

endmodule