v2p_qdr2_input_buffer.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//**
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
//**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
//**              provided to you \"as is\". Xilinx and its licensors make and you 
//**              receive no warranties or conditions, express, implied, statutory 
//**              or otherwise, and Xilinx specifically disclaims any implied 
//**              warranties of merchantability, non-infringement, or fitness for a 
//**              particular purpose. Xilinx does not warrant that the functions 
//**              contained in these designs will meet your requirements, or that the
//**              operation of these designs will be uninterrupted or error free, or 
//**              that defects in the Designs will be corrected. Furthermore, Xilinx 
//**              does not warrant or make any representations regarding use or the 
//**              results of the use of the designs in terms of correctness, accuracy, 
//**              reliability, or otherwise. 
//**
//**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
//**              liable for any loss of data, lost profits, cost or procurement of 
//**              substitute goods or services, or for any special, incidental, 
//**              consequential, or indirect damages arising from the use or operation 
//**              of the designs or accompanying documentation, however caused and on 
//**              any theory of liability. This limitation will apply even if Xilinx 
//**              has been advised of the possibility of such damage. This limitation 
//**              shall apply not-withstanding the failure of the essential purpose of 
//**              any limited remedies herein. 
//**
//*****************************************************************************************

`timescale 1 ns/1 ps

module v2p_qdr2_input_buffer ( qdr2_in, read_data_in );
                               
 input qdr2_in;
 output read_data_in;

IBUF_HSTL_I_DCI_18 Data_inp_buf (.I(qdr2_in), .O(read_data_in) );

 endmodule