v2p_qdr2_input_buffer.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 45 行

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`timescale 1 ns/1 ps

module v2p_qdr2_input_buffer ( qdr2_in, read_data_in );
                               
 input qdr2_in;
 output read_data_in;

IBUF_HSTL_I_DCI_18 Data_inp_buf (.I(qdr2_in), .O(read_data_in) );

 endmodule