qdr2_fsm_access.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//**
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
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//**              receive no warranties or conditions, express, implied, statutory 
//**              or otherwise, and Xilinx specifically disclaims any implied 
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//**              particular purpose. Xilinx does not warrant that the functions 
//**              contained in these designs will meet your requirements, or that the
//**              operation of these designs will be uninterrupted or error free, or 
//**              that defects in the Designs will be corrected. Furthermore, Xilinx 
//**              does not warrant or make any representations regarding use or the 
//**              results of the use of the designs in terms of correctness, accuracy, 
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//**
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//*****************************************************************************************

`timescale 1 ns/1 ps

module qdr2_fsm_access (CLK,
                        RESET,
                        USER_W_n,
                        USER_R_n,
                        WRITE_E,
                        READ_E,
                        CLK_A_RD,
                        MUX_ADR_RD);
                      
 input CLK;
 input RESET;
 input USER_W_n;
 input USER_R_n;
 output WRITE_E;
 output READ_E;
 input CLK_A_RD;
 output MUX_ADR_RD;
 
 parameter [2:0] Idle = 0, Write = 1, AfterWrite = 2, Read = 3, AfterRead = 4;
 reg [2:0] State;
 
 reg WRITE_E; 
 reg READ_E;  
 reg ST_RD;
 reg ST_WR;
 
 always @(posedge CLK or posedge RESET)
  begin: NEXT_CURR
   if (RESET) 
    State <= Idle;
   else
    case(State)
    
     Idle: begin
      if (!USER_W_n)
       State <= Write;
      else if (!USER_R_n)
       State <= Read;
      else
       State <= Idle;
    end
    
   Write: begin
    if (!USER_R_n)
     State <= Read;
    else
     State <= AfterWrite; 
    end
    
   AfterWrite: begin
    if (!USER_W_n)
     State <= Write;
    else if (!USER_R_n)
     State <= Read; 
    else 
     State <= Idle;
    end
    
   Read: begin
    if (!USER_W_n)
     State <= Write;
    else
     State <= AfterRead;
    end
    
   AfterRead: begin
    if (!USER_W_n)
     State <= Write;
    else if (!USER_R_n)
     State <= Read; 
    else
     State <= Idle;   
    end
   endcase
  end
  
 always @(posedge CLK)
  begin: SEQ
   if (RESET) begin
    WRITE_E <= 1'b1; // Write command high at reset
    READ_E <= 1'b1; // Read command high at reset
   end
   else begin
    WRITE_E <= ST_WR;
    READ_E <= ST_RD;
   end
  end 
   
 always @(State)
  begin: OUT_LOGIC
   case (State)
   
    Idle: begin
     ST_WR <= 1'b1;
     ST_RD <= 1'b1;
    end
    Write: begin
     ST_WR <= 1'b0;                  
     ST_RD <= 1'b1; 
    end
    AfterWrite: begin  
     ST_WR <= 1'b1; 
     ST_RD <= 1'b1;  
    end
    Read: begin              
     ST_WR <= 1'b1;  
     ST_RD <= 1'b0;   
    end 
    AfterRead: begin              
     ST_WR <= 1'b1;  
     ST_RD <= 1'b1;   
    end
    default: begin
     ST_WR <= 1'b1;
     ST_RD <= 1'b1;
    end  
   endcase
  end
  
//****************************************************************************************************************
// Register READ_E for address multiplexing
//****************************************************************************************************************  
  
FD FD_MUX_ADR_RD (.Q(MUX_ADR_RD), .D(ST_RD), .C(CLK_A_RD));

endmodule