qdr2_clocks.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
--**
--**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
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--**              contained in these designs will meet your requirements, or that the
--**              operation of these designs will be uninterrupted or error free, or 
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--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
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--**
--*****************************************************************************************

--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on



entity qdr2_clocks is
 port ( 		USER_CLK 		: in std_logic;
		USER_CLK_N 		: in std_logic;
		RESET 		: in std_logic;
        		CLK_BUF 		: out std_logic;
		GCLK0 		: out std_logic;
        		GCLK90 		: out std_logic;
		GCLK180 		: out std_logic;
        		GCLK270 		: out std_logic;
            		CLKDIV2		: out std_logic;
            		LOCKED_DCM 		: out std_logic
        
        );

end qdr2_clocks;

architecture qdr2_clocks_arch of qdr2_clocks is

--***********************************************
--* Components declaration
--***********************************************
 component DCM
  port ( CLKIN : in std_logic;
         CLKFB : in std_logic;
         DSSEN : in std_logic;
         PSINCDEC : in std_logic;
         PSEN : in std_logic;
         PSCLK : in std_logic;
         RST : in std_logic;
         CLK0 : out std_logic;
         CLK90 : out std_logic;
         CLK180 : out std_logic;
         CLK270 : out std_logic;
         CLK2X : out std_logic;
         CLK2X180 : out std_logic;
         CLKDV : out std_logic;
         CLKFX : out std_logic;
         CLKFX180 : out std_logic;
         LOCKED : out std_logic;
         PSDONE : out std_logic;
         STATUS : out std_logic_vector(7 downto 0));
 end component;

 component BUFG
  port ( I : in std_logic;
         O : out std_logic);
 end component;

component IBUFGDS_LVDS_25
port (O : out std_logic;
      I : in std_logic; 
      IB : in std_logic);
end component;

--***********************************************
--* Signals and constants declaration
--***********************************************

 signal GND : std_logic := '0';
 signal LOCKED_DCM_PRI : std_logic;
 signal LOCKED_DCM_SEC : std_logic;
 signal CLK0E : std_logic;
 signal CLK90E : std_logic;
 signal CLK180E : std_logic;
 signal CLK270E : std_logic;

 signal CLK0E_BUF : std_logic;
 signal CLK90E_BUF : std_logic;
 signal CLK270E_BUF : std_logic;
 signal CLK180E_BUF : std_logic;	
 signal CLK_DV_BUF : std_logic;
 signal CLK_BUF_val : std_logic;
 
	
begin
 
CLK_BUF <= CLK_BUF_val; 
GCLK0 	<= CLK0E;
GCLK90 	<= CLK90E;
GCLK180 <= CLK180E;
GCLK270 <= CLK270E;

LOCKED_DCM <= LOCKED_DCM_PRI;

 INST_DCM_TOMEMORY : DCM port map (
                             CLKIN => CLK_BUF_val,
                             CLKFB => CLK0E,
                             DSSEN => GND,
                             PSINCDEC => GND,
                             PSEN => GND,
                             PSCLK => GND,
                             RST => RESET,
                             CLK0 => CLK0E_BUF,
                             CLK90 => CLK90E_BUF,
                             CLK180 => CLK180E_BUF,
                             CLK270 => CLK270E_BUF,
                             CLK2X180 => open,
                             CLK2X => open,
                             CLKDV => open,
                             CLKFX => open,
                             CLKFX180 => open,
                             LOCKED => LOCKED_DCM_PRI,
                             PSDONE => open,
                             STATUS => open);


-- The test design requires CLK0 /2. The number of direct clock interconnect per DCM is 4,
-- and CLK0 through 270 are using these clocks. 
-- An addition DCM is used to generate CLK0/2 in order to maintain low clock tree skew.                                                                                          



 BUFG_Sec_0  : BUFG port map ( I => CLK0E_BUF,
                               O => CLK0E);

 BUFG_Sec_90 : BUFG port map ( I => CLK90E_BUF,
                               O => CLK90E);

 BUFG_Sec_180  : BUFG port map ( I => CLK180E_BUF,
                               O => CLK180E);

 BUFG_Sec_270 : BUFG port map ( I => CLK270E_BUF,
                               O => CLK270E);


 --BUFG_CLKDIV2 : BUFG port map ( I => CLK_DV_BUF,
--                               O => CLKDIV2);

IBUFG_GENE : IBUFGDS_LVDS_25 port map  ( O => CLK_BUF_val , I => USER_CLK , IB => USER_CLK_N);




end qdr2_clocks_arch;