qdr2_fsm_access.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
--**
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--**              contained in these designs will meet your requirements, or that the
--**              operation of these designs will be uninterrupted or error free, or 
--**              that defects in the Designs will be corrected. Furthermore, Xilinx 
--**              does not warrant or make any representations regarding use or the 
--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
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--**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
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--*****************************************************************************************

--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity qdr2_fsm_access is

port ( CLK 		: in std_logic;
       RESET 	: in std_logic;
       USER_W_n 	: in std_logic;
       USER_R_n 	: in std_logic;
       WRITE_E 	: out std_logic;
       READ_E 	: out std_logic;
       CLK_A_RD 	: in std_logic;
       MUX_ADR_RD : out std_logic );

end qdr2_fsm_access;

architecture qdr2_fsm_access_arch of qdr2_fsm_access is

--***********************************************
--* Components declaration
--***********************************************

 component FD
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic);
 end component;

--***********************************************
--* Signals and constants declaration
--***********************************************

attribute syn_keep : boolean;
type s_m is (Idle, Write, AfterWrite, Read, AfterRead);
signal State : s_m;


 signal ST_WR : std_logic;
 signal ST_RD : std_logic;
attribute syn_keep of CLK : signal is true;

begin
 
-- CLK <= not( CLK0 ); 

  state_reg : PROCESS
  BEGIN
   WAIT UNTIL CLK'event and CLK = '1';
    IF (RESET = '1')  THEN
                 State <= Idle;
    ELSE
      CASE State is
       WHEN Idle => 
          IF USER_W_n = '0' THEN
                 State <= Write;
          ELSIF USER_R_n = '0' THEN
                 State <= Read;
          ElSE
                 State <= Idle;
          END IF;

       WHEN Write =>
          IF USER_R_n = '0' THEN
                 State <= Read;
          ElSE
                 State <= AfterWrite;
          END IF;

       WHEN AfterWrite =>
          IF USER_W_n = '0' THEN
                 State <= Write;
          ELSIF USER_R_n = '0' THEN
                 State <= Read;
          ElSE
                 State <= Idle;
          END IF;

       WHEN Read =>
          IF USER_W_n = '0' THEN
                 State <= Write;
          ElSE
                 State <= AfterRead;
          END IF;

       WHEN AfterRead =>
          IF USER_W_n = '0' THEN
                 State <= Write;
          ELSIF USER_R_n = '0' THEN
                 State <= Read;
          ElSE
                 State <= Idle;
          END IF;

      END CASE;
    END IF;
  END PROCESS; -- state_reg

  enable_reg : PROCESS
  BEGIN
    WAIT UNTIL CLK'event and CLK = '1';
      IF (RESET = '1')  THEN
          WRITE_E <= '1';
          READ_E <= '1';
      ELSE
          WRITE_E <= ST_WR;
          READ_E <= ST_RD;
      END IF;
  END PROCESS;   -- enable_reg

  OUT_LOGIC : PROCESS ( State )
  BEGIN
     CASE State is
       WHEN Idle =>
             ST_WR <= '1';
             ST_RD <= '1';
       WHEN Write =>
             ST_WR <= '0';
             ST_RD <= '1';
       WHEN AfterWrite =>
             ST_WR <= '1';
             ST_RD <= '1';
       WHEN Read =>
             ST_WR <= '1';
             ST_RD <= '0';
       WHEN AfterRead =>
             ST_WR <= '1';
             ST_RD <= '1';
       WHEN OTHERS =>
             ST_WR <= '1';
             ST_RD <= '1';
     END CASE;
 END PROCESS; -- OUT LOGIC

 FD_MUX_ADR_RD : FD port map (
                            Q => MUX_ADR_RD,
                            D => ST_RD,
                            C => CLK_A_RD );
								  
end qdr2_fsm_access_arch;