v2p_qdr2_input_buffer.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
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--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
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--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
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--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity v2p_qdr2_input_buffer is

port ( qdr2_in : in std_logic;
       read_data_in : out std_logic );

end v2p_qdr2_input_buffer;

architecture v2p_qdr2_input_buffer_arch of v2p_qdr2_input_buffer is

--***********************************************
--* Components declaration
--***********************************************

component IBUF_HSTL_I_DCI_18
 port ( O : out std_logic;
        I : in std_logic );
end component;


begin

 Data_inp_buf : IBUF_HSTL_I_DCI_18 port map
                  ( I => qdr2_in,
                    O => read_data_in );
								  
end v2p_qdr2_input_buffer_arch;