counter_262144.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity counter_262144 is
port ( COut2 : out std_logic_vector(17 downto 0);
       inc   : in std_logic;
       reset : in std_logic);
end counter_262144 ;

architecture arc_counter_262144  of counter_262144  is 
signal counter2 		  : std_logic_vector(17 downto 0);
signal counter      : std_logic_vector(17 downto 0);

begin

--counter2_val <= counter2;


counter <=   "000000000000000000" when ((reset = '1') or (counter2 = "000000000000011111")) else
             (counter2 + '1');  

process (inc)
begin
	if inc'event and inc ='1' then
		if reset = '1' or counter2 = "000000000000011111" then
		counter2 <= "000000000000000000";
		else
		counter2 <= counter;
		end if;
	end if;
end process;
	
--process (inc)
--begin
--	if inc'event and inc ='1' then
	COut2 <= counter2;	
--	end if;
--end process;
	
end arc_counter_262144 ;