delay.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 46 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity delay is 
port ( Si_In : in std_logic;
       Si_Out: out std_logic;
       Clock : in std_logic;
       Reset : in std_logic);
end delay;

architecture arc_delay of delay is
signal counter : std_logic_vector(9 downto 0);
begin

--*****************************************************************************************
-- Counter used to delay the start of the test program
--*****************************************************************************************

process(Clock)
begin
	if Clock'event and Clock ='0' then
		if Reset = '1' then
		   counter <= "0000000000";
  		   Si_Out <= '0';
  		else 
  		   if Si_In = '1' then
  		      if counter = 16#3FF# then
  		      Si_Out <='1';
  		      else
  		      Si_Out <= '0';
  		      counter <= counter +16#1#;
  		      end if;
  		    end if;
  		 end if;
  	end if;
 end process;
  		 
end arc_delay;