cq_delay.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
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--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity cq_delay is

port ( clk_in : in std_logic;
       sel_in : in std_logic_vector (4 downto 0);
       clk_out : out std_logic );

end cq_delay;

architecture cq_delay_arch of cq_delay is

attribute syn_hier : string;
attribute syn_hier of cq_delay_arch: architecture is "hard";

--***********************************************
--* Components declaration
--***********************************************

 component LUT4
   generic (
      INIT  :  bit_vector(15 downto 0) := x"0000" );
  port ( O : out STD_ULOGIC;
        I0 : in STD_ULOGIC; 
        I1 : in STD_ULOGIC;
        I2 : in STD_ULOGIC;
        I3 : in STD_ULOGIC );
 end component;

--***********************************************
--* Signals and constants declaration
--***********************************************

 signal delay1 : std_logic;
 signal delay2 : std_logic;
 signal delay3 : std_logic;
 signal delay4 : std_logic;
 signal delay5 : std_logic;
 signal high : std_logic := '1';

begin
 
 one : LUT4 generic map (INIT => x"f3c0")
            port map ( I0 => high,
                       I1 => sel_in(4),
                       I2 => delay5,
                       I3 => clk_in,
                       O => clk_out );

 two : LUT4 generic map (INIT => x"ee22")
            port map ( I0 => clk_in,
                       I1 => sel_in(2),
                       I2 => high,
                       I3 => delay3,
                       O => delay4 );

 three : LUT4 generic map (INIT => x"e2e2")
            port map ( I0 => clk_in,
                       I1 => sel_in(0),
                       I2 => delay1,
                       I3 => high,
                       O => delay2 );

 four : LUT4 generic map (INIT => x"ff00")
            port map ( I0 => high,
                       I1 => high,
                       I2 => high,
                       I3 => clk_in,
                       O => delay1 );

 five : LUT4 generic map (INIT => x"f3c0")
            port map ( I0 => high,
                       I1 => sel_in(3),
                       I2 => delay4,
                       I3 => clk_in,
                       O => delay5 );

 six : LUT4 generic map (INIT => x"e2e2")
            port map ( I0 => clk_in,
                       I1 => sel_in(1),
                       I2 => delay2,
                       I3 => high,
                       O => delay3 );

end cq_delay_arch;