qdr2_reset.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

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--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
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--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
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--* Library declaration
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity QDR2_RESET is

port ( ML365_RESET : in std_logic;
       USER_RESET : out std_logic );

end QDR2_RESET;

architecture QDR2_RESET_arch of QDR2_RESET is
component IBUF_LVCMOS25
  port( O : out std_logic;
        I : in std_logic );
 end component;

signal RESET : std_logic;
begin
 
 USER_RESET <= not( RESET );

 INST_IBUF : IBUF_LVCMOS25 port map  (O => RESET, 
				    I => ML365_RESET);



end QDR2_RESET_arch;