counter_4.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;




entity counter_4 is
port(counter : out std_logic_vector(1 downto 0);
     inclock : in std_logic;
     reset   : in std_logic);
end counter_4;

architecture arc_counter_4 of counter_4 is
signal counter_val : std_logic_vector(1 downto 0);
begin
counter <= counter_val;
process (inclock)
begin
	if inclock'event and inclock ='1' then
		if reset = '1' then
		counter_val <= "00";
		else
		counter_val <= counter_val + "01" ;
		end if;
	end if;
end process;

end arc_counter_4;