qdr2_qbit_cq.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
--**
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--*****************************************************************************************

--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity qdr2_qbit_cq is

generic (
   -- Constant Parameters
   addr_bits : INTEGER :=     18;
   mem_sizes : INTEGER := 524287
   );

port ( reset : in std_logic;
       cq : in std_logic;
       cq1 : in std_logic;
       qdr2_q : in std_logic;
       CE_R_FB0 : in std_logic;
       CE_R_FB1 : in std_logic;
       CE_R_FB2 : in std_logic;
       CE_R_FB3 : in std_logic;
       fbit_0 : out std_logic;
       fbit_1 : out std_logic;
       fbit_2 : out std_logic;
       fbit_3 : out std_logic );

end qdr2_qbit_cq;

architecture qdr2_qbit_cq_arch of qdr2_qbit_cq is

--***********************************************
--* Components declaration
--***********************************************

component FDCE
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic;
        CE : in std_logic;
        CLR : in std_logic );
end component;

component v2p_qdr2_input_buffer
 port ( qdr2_in : in std_logic;
        read_data_in : out std_logic );
end component;


--***********************************************
--* Signals and constants declaration
--***********************************************

 signal fbit : std_logic_vector (3 downto 0);
 signal async_clr : std_logic;
 signal q : std_logic;
 signal cqn : std_logic;
 signal cq1n : std_logic;

begin
 
 async_clr <= reset; 
 fbit_0 <= fbit(0); 
 fbit_1 <= fbit(1); 
 fbit_2 <= fbit(2); 
 fbit_3 <= fbit(3); 
 cqn <= not(cq); 
 cq1n <= not(cq1); 

 fbit0 : FDCE port map (
                   Q => fbit(0),
                   C => cq1n,
                   CE => CE_R_FB0,
                   CLR => async_clr,
                   D => q );

 fbit1 : FDCE port map (
                   Q => fbit(1),
                   C => cq,
                   CE => CE_R_FB1,
                   CLR => async_clr,
                   D => q );

 fbit2 : FDCE port map (
                   Q => fbit(2),
                   C => cq1n,
                   CE => CE_R_FB2,
                   CLR => async_clr,
                   D => q );

 fbit3 : FDCE port map (
                   Q => fbit(3),
                   C => cq,
                   CE => CE_R_FB3,
                   CLR => async_clr,
                   D => q );

--q <= qdr2_q;

v2p_qdr2_iob0  : v2p_qdr2_input_buffer  port map
			( qdr2_in=> qdr2_q, 
			  read_data_in => q ); 


end qdr2_qbit_cq_arch;