qdr2_transfer_done.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
--**
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--*****************************************************************************************

--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity qdr2_transfer_done is

port ( 
	 clk0 : in std_logic;
       clk90 : in std_logic;
	 clk180 : in std_logic;
       clk270 : in std_logic;
       reset : in std_logic;
       reset90 : in std_logic;
       reset180 : in std_logic;
       reset270 : in std_logic;
       cq_div : in std_logic;
       transfer_done0 : out std_logic;
       transfer_done1 : out std_logic;
       transfer_done2 : out std_logic;
       transfer_done3 : out std_logic );

end qdr2_transfer_done;

architecture qdr2_transfer_done_arch of qdr2_transfer_done is

attribute syn_hier : string;
attribute syn_hier of qdr2_transfer_done_arch: architecture is "hard";

--***********************************************
--* Components declaration
--***********************************************

 component LUT2
   generic(
      INIT  :  bit_vector(3 downto 0) := x"0" );
  port ( O : out STD_ULOGIC;
        I0 : in STD_ULOGIC; 
        I1 : in STD_ULOGIC );
 end component;

 component LUT3
   generic(
      INIT  :  bit_vector(7 downto 0) := x"00" );
  port ( O : out STD_ULOGIC;
        I0 : in STD_ULOGIC; 
        I1 : in STD_ULOGIC; 
        I2 : in STD_ULOGIC );
 end component;

 component FDR
  port ( Q : out std_logic;
         C : in std_logic;
         D : in std_logic;
         R : in std_logic );
 end component;

 component FD
  port ( Q : out std_logic;
         C : in std_logic;
         D : in std_logic );
 end component;

--***********************************************
--* Signals and constants declaration
--***********************************************

attribute syn_keep : boolean;
 signal transfer_done_int : std_logic_vector (3 downto 0);
 signal transfer_done0_clk0 : std_logic;
 signal transfer_done0_clk90 : std_logic;
 signal transfer_done0_clk180 : std_logic;
 signal transfer_done0_clk270 : std_logic;
 signal transfer_done1_clk90 : std_logic;
 signal transfer_done1_clk270 : std_logic;
 signal transfer_done2_clk90 : std_logic;
 signal transfer_done2_clk270 : std_logic;
 signal transfer_done3_clk90 : std_logic;
 signal transfer_done3_clk270 : std_logic;
 signal sync_rst_xdone0_ck0 : std_logic;
 signal sync_rst_xdone0_ck180 : std_logic;
 signal sync_rst_clk90 : std_logic;
 signal sync_rst_clk270 : std_logic;


begin
 
 sync_rst_xdone0_ck0 <= reset or transfer_done0_clk0;
 sync_rst_xdone0_ck180 <= reset180 or transfer_done0_clk180;
 transfer_done0 <= transfer_done_int(0);
 transfer_done1 <= transfer_done_int(1);
 transfer_done2 <= transfer_done_int(2);
 transfer_done3 <= transfer_done_int(3);

 xdone0 : LUT2 generic map (INIT => x"e")
            port map ( I0 => transfer_done0_clk90,
                       I1 => transfer_done0_clk270,
                        O => transfer_done_int(0) );

 xdone1 : LUT2 generic map (INIT => x"e")
            port map ( I0 => transfer_done1_clk90,
                       I1 => transfer_done1_clk270,
                        O => transfer_done_int(1) );

 xdone2 : LUT2 generic map (INIT => x"e")
            port map ( I0 => transfer_done2_clk90,
                       I1 => transfer_done2_clk270,
                        O => transfer_done_int(2) );

 xdone3 : LUT2 generic map (INIT => x"e")
            port map ( I0 => transfer_done3_clk90,
                       I1 => transfer_done3_clk270,
                        O => transfer_done_int(3) );

 xdone0_clk0 : FDR port map (
                       Q => transfer_done0_clk0,
                       C => clk0,
                       R => sync_rst_xdone0_ck0,
                       D => cq_div );

 xdone0_clk90 : FDR port map (
                       Q => transfer_done0_clk90,
                       C => clk90,
                       R => sync_rst_clk90,
                       D => transfer_done0_clk0 );

 xdone0_clk180 : FDR port map (
                       Q => transfer_done0_clk180,
                       C => clk180,
                       R => sync_rst_xdone0_ck180,
                       D => cq_div );

 xdone0_clk270 : FDR port map (
                       Q => transfer_done0_clk270,
                       C => clk270,
                       R => sync_rst_clk270,
                       D => transfer_done0_clk180 );

 xdone0_rst90 : LUT3 generic map (INIT => x"fe")
            port map ( I0 => reset90,
                       I1 => transfer_done0_clk270,
                       I2 => transfer_done0_clk90,
                        O => sync_rst_clk90 );

 xdone0_rst270 : LUT3 generic map (INIT => x"fe")
            port map ( I0 => reset270,
                       I1 => transfer_done0_clk270,
                       I2 => transfer_done0_clk90,
                        O => sync_rst_clk270 );

 xdone1_clk90 : FD port map (
                       Q => transfer_done1_clk90,
                       C => clk90,
                       D => transfer_done0_clk270 );

 xdone1_clk270 : FD port map (
                       Q => transfer_done1_clk270,
                       C => clk270,
                       D => transfer_done0_clk90 );

 xdone2_clk90 : FD port map (
                       Q => transfer_done2_clk90,
                       C => clk90,
                       D => transfer_done1_clk270 );

 xdone2_clk270 : FD port map (
                       Q => transfer_done2_clk270,
                       C => clk270,
                       D => transfer_done1_clk90 );

 xdone3_clk90 : FD port map (
                       Q => transfer_done3_clk90,
                       C => clk90,
                       D => transfer_done2_clk270 );

 xdone3_clk270 : FD port map (
                       Q => transfer_done3_clk270,
                       C => clk270,
                       D => transfer_done2_clk90 );

end qdr2_transfer_done_arch;