qdr2_cq_div.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
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--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity qdr2_cq_div is

port ( cq : in std_logic;
       cq1 : in std_logic;
       rst_cq_div : in std_logic;
       cq_tranfert_col0 : out std_logic;
       cq_tranfert_col1 : out std_logic );

end qdr2_cq_div;

architecture qdr2_cq_div_arch of qdr2_cq_div is

--***********************************************
--* Components declaration
--***********************************************

 component FD
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic);
 end component;

--***********************************************
--* Signals and constants declaration
--***********************************************

 signal cqn : std_logic;
 signal cq1n : std_logic;

begin
 
 cqn <= not( cq );
 cq1n <= not( cq1 );

 col1_transfert : FD port map (
                       Q => cq_tranfert_col0,
                       D => rst_cq_div,
                       C => cq1n );

 col0_transfert : FD port map (
                       Q => cq_tranfert_col1,
                       D => rst_cq_div,
                       C => cqn );
								  
end qdr2_cq_div_arch;