qdr_lc_top.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

g3: for i3 in 0 to 35 generate
FD_REFDATA_ST2 : FD port map  ( Q => FD2_Reference_Data(i3), D => FD1_Reference_Data(i3), C => GCLK90); 
end generate;   

g4: for i4 in 0 to 35 generate
FD_REFDATA_ST3 : FD port map  ( Q => FD3_Reference_Data(i4), D => FD2_Reference_Data(i4), C => GCLK90); 
end generate;  

--*****************************************************************************************
-- Instantiate QDR-II Memory Interface clocking module
--*****************************************************************************************

QDR_interface_clocks : qdr2_clocks 
port map (  USER_CLK 	=> CLK200,
            USER_CLK_N  => CLK200N,
            RESET 	=> USER_RESET, 
            CLK_BUF 	=> CLK_BUF,
            GCLK0 	=> GCLK0,
            GCLK90 	=> GCLK90,
            GCLK180 	=> GCLK180,
            GCLK270 	=> GCLK270,
            CLKDIV2 	=> CLK_DIV2,
            LOCKED_DCM 	=> DCM_LOCKED );
		
--*****************************************************************************************
-- Instantiate QDR-II Memory Interface 
--*****************************************************************************************

QDR_Interface_B : qdr2_burst_4_body
port map ( USER_DWL 			   => Cout_WDataL, 
           USER_DWH 			   => Cout_WDataH,
           USER_Q 			   => DataR, 
           USER_A_READ 		 	=> AddrR,
           USER_A_WRITE 			=> AddrW,
           CLK_BUF 			   => CLK_BUF,
           CLK0E 			   => GCLK0,
           CLK90E 			   => GCLK90,
           CLK180E 			   => GCLK180,
           CLK270E 			   => GCLK270,
           LOCKED_DCM_PRI 	=> DCM_LOCKED,
           USER_R_n 		     => R_n, 
           USER_W_n 			   => W_n,
           USER_BW_n 			   => "0000",
           USER_RESET 		   => DCM_LOCKED_n,
           USER_DATA_VALID => UserDataValid,
--           USER_WRITE_E 		 => WCtrl_BUF,
--           USER_READ_E 			 => RCtrl_BUF,
           QDR_Q 			   => mem_Q_val,
           QDR_D 			   => mem_D_val,
           QDR_SA 			   => mem_SA_val,
           QDR_R_n 			   => mem_R_n,
           QDR_W_n 			   => mem_W_n,
           QDR_BW_n 			   => mem_BW_n,
           QDR_K 			   => mem_K,
           QDR_K_n 			   => mem_K_n,
           QDR_C 			   => mem_C,
           QDR_C_n 			   => mem_C_n,
           QDR_CQ 			   => mem_CQ,
           QDR_CQ_n 			   => mem_CQ_n,
           QDR_R_n_ext 			 => mem_R_n_ext,
           QDR_R_n_int 			 => mem_R_n_int,
           TEST_RESET_0			 => Reset_CLK0
--         ,TEST_RESET_90 		=> Reset_CLK90,
--           TEST_CAPTURE_D0 => D0_capture_BUF
           );   
                                    
--*****************************************************************************************
-- Reset module, specific to ML365 
--*****************************************************************************************                                    
                                                        
ML365_RESET : QDR2_RESET port map ( ML365_RESET => Reset,
			    USER_RESET => USER_RESET);
			    

--*****************************************************************************************
-- Generate data using a counter, out of CLK0
--*****************************************************************************************                                   
WordGene_H0 : counter_4  
port map(			  counter => Counter_outH ,
                          inclock => GCLK0,
                          reset => ResetCount);   
                     
Concat_Write_High : concat2to36Data
port map  ( 			  inclock => GCLK0,
                          Sortie  => Cout_WDataH,
                          counter => Counter_outH); 
   	    
WordGene_L0 : counter_4
port map  (			 counter => Counter_outL,
                         inclock => GCLK0,
                         reset   => ResetCount);   
                     
Concat_Write_Low : concat2to36Data
port map ( 			 inclock => GCLK0,
                         Sortie  => Cout_WDataL,
                         counter => Counter_outL); 


--*****************************************************************************************
-- Generate addresses using a conter, from address 0, out of CLK0/2 and ~CLK0/2
--*****************************************************************************************  	    

AddrGeneR : counter_262144
port map  ( COut2 => AddrR, 
            inc   => GCLK0_2,
            reset => ResetCount );   
                          
AddrGeneW : counter_262144 
port map ( COut2 => AddrW,
           inc   => GCLK0_2_n,
           reset => ResetCount );     

--*****************************************************************************************
-- Delay at power up to leave time for the QDR II SRAM to lock its DLL
--*****************************************************************************************  
StartTest :delay 
port map( 		Si_In  => DCM_LOCKED,
                Si_Out => ThisIsAGo,
                Clock  => GCLK0,
                Reset  => Reset_CLK0);    

--*****************************************************************************************
-- Generation of the reference data to compare written adn read data
--*****************************************************************************************               
Data_Check_Gene : counter_4 
port map ( counter => To_concatenate, 
           inclock => GCLK90,
           reset   => FD_UserDataValid_n);   
                     
Concatenate_Test :  concat2to36Data  
port map  (inclock => GCLK90,
	   Sortie  => Reference_Data,
	   counter => To_concatenate);   

--INST_OBUF_UDV 			: OBUF_LVDCI_25  port map(O => UDV , I => FD_UserDataValid); 
--INST_OBUF_WOR 			: OBUF_LVDCI_25  port map(O => WCtrl , I => WCtrl_BUF);
--INST_OBUF_REA 			: OBUF_LVDCI_25  port map(O => RCtrl , I => RCtrl_BUF);
--INST_OBUF_DCM 			: OBUF_LVDCI_25  port map(O => DCM_LCK , I => DCM_LCK_BUF); -- This is a test signal, use with ML365 only
--INST_OBUF_FIFO_D0 			: OBUF_LVDCI_25  port map(O => D0_FIFO , I => FD_Data_R(0));
--INST_OBUF_REF_D0 			: OBUF_LVDCI_25  port map(O => D0_Reference , I => Reference_Data_BUF);
--INST_OBUF_CAPT_D0 			: OBUF_LVDCI_25  port map(O => D0_capture , I =>D0_capture_BUF); 
INST_OBUF_Result_D0 			: OBUF_LVDCI_25  port map(O => Result_Reg , I => Result_BUF); 
--INST_OBUF_TEST_CLOCK 			: OBUF_LVDCI_25  port map(O => CLOCK_TEST , I => CLK_DIV2);

--INST_QDR_OBUF_A_R : OBUF_HSTL_II_18  port map(O => A_R , I => '1'); 
--INST_QDR_OBUF_A_W : OBUF_HSTL_II_18  port map(O => A_W , I => '1');
--INST_QDR_OBUF_C_R : OBUF_HSTL_II_18  port map(O => C_R , I => '1');
--INST_QDR_OBUF_C_W : OBUF_HSTL_II_18  port map(O => C_W , I => '1');
--INST_QDR_OBUF_U28 : OBUF_HSTL_II_18  port map(O => U28 , I => '1');
--INST_QDR_OBUF_H26 : OBUF_HSTL_II_18  port map(O => H26 , I => '1');

process (GCLK0)
begin
 if GCLK0'event and GCLK0 = '1' then
    if Reset_CLK0 ='1' then
    GCLK0_2 <= '0' ;
    else 
    GCLK0_2 <= (not GCLK0_2);
    end if;
  end if;
end process;

--*****************************************************************************************
-- Comparator of read data
--*****************************************************************************************
process (GCLK0)
begin
 if GCLK0'event and GCLK0 = '1' then
    if Reset_CLK0 ='1' then
	Result <= '0';
    else
    	if FD_UserDataValid = '1' and (FD_Data_R(71 downto 36) = Reference_Data) and (FD_Data_R(35 downto 0) = Reference_Data) then
    	Result <= '1';
    	else
    	Result <= '0';
    	end if;
    end if;
  end if;
end process;

process (GCLK0)
begin
 if GCLK0'event and GCLK0 = '1' then
   Result_BUF <= Result;
   Reference_Data_BUF <= Reference_Data(0);
 end if;
end process;
 
 
--*****************************************************************************************
-- Synchronous state machine   
--*****************************************************************************************  

state_machine : process(DCM_LOCKED , ThisIsAGo,CurrentState,AddrW,AddrR,W_n,R_n,Status_Ctrl_Operation)
begin   
NextState <= Start ;
	case CurrentState is
	when Start =>
		if DCM_LOCKED = '1' then
		NextState <= GetReady;
		else
		NextState <= Start;
		end if;
	when GetReady =>
		if ThisIsAGo = '1' then
			if Status_Ctrl_Operation = '1' then
			NextState <= ReadCycle;
			else
			NextState <= WriteCycle;
			end if;
		else
		NextState <= GetReady;
		end if;
	when WriteCycle =>
		if  (AddrW = "000000000000011111"  and  R_n = '1' ) then
		NextState <= Start;
		else
		NextState <= WriteCycle;
		end if;
	when ReadCycle =>
		if AddrR = "000000000000011110" and W_n = '1' then
		NextState <= Start;
		else
		NextState <= ReadCycle;
		end if;
	end case;
   
end process;

process (GCLK0)
begin
 if GCLK0'event and GCLK0 = '1' then
	if Reset_CLK0 = '1' then
 	CurrentState <= Start;
  	else
   	CurrentState <= NextState;
   	end if;
 end if;
end process;

output_logic : process (CurrentState,Status_Ctrl_Operation_buf)
begin
case CurrentState is
	when Start=>
		ResetCount <= '1';
		R_n <= '1';
		W_n <= '1';
		Status_Ctrl_Operation <= Status_Ctrl_Operation_buf;
	when GetReady =>
		ResetCount <= '1';
		R_n <= '1';
		W_n <= '1';
		Status_Ctrl_Operation <= Status_Ctrl_Operation_buf;
	when WriteCycle =>
		ResetCount <= '0';
		R_n <= '1';
		W_n <= '0';
		Status_Ctrl_Operation <= '1';
	when ReadCycle =>
		ResetCount <= '0';
		R_n <= '0';
		W_n <= '1';
		Status_Ctrl_Operation <= '0';
	when others =>
		ResetCount <= '1';
		R_n <= '1';
		W_n <= '0';
		Status_Ctrl_Operation <= '0';
end case;
end process;

process (GCLK0)
begin
 if GCLK0'event and GCLK0 = '1' then
    if Reset_CLK0 ='1' then
    Status_Ctrl_Operation_buf <= '0';
    else
    Status_Ctrl_Operation_buf <= Status_Ctrl_Operation;
    end if;
 end if;
end process;

end arc_QDR_LC_TOP;