📄 qdr2_burst_4_body.vhd
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--*****************************************************************************************
--**
--** www.xilinx.com Copyright c) 1984-2004 Xilinx, Inc. All rights reserved
--**
--** QDR(tm)-II SRAM Virtex(tm)-II Interface VHDL instanciation
--**
--*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you \"as is\". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- This module is the top level architecture for the memory interface design.
-- The signals connections are describled in the application note.
-- The ports naming convention is as follows:
-- - user side: USER_INSTNAME
-- - memory side: QDR_INSTNAME
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
entity qdr2_burst_4_body is
generic (
-- Constant Parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 36;
mem_sizes : INTEGER := 524287
);
port ( USER_DWL : in std_logic_vector(data_bits-1 downto 0);
USER_DWH : in std_logic_vector(data_bits-1 downto 0);
USER_Q : out std_logic_vector(71 downto 0);
CLK_BUF : in std_logic;
CLK0E : in std_logic;
CLK90E : in std_logic;
CLK180E : in std_logic;
CLK270E : in std_logic;
LOCKED_DCM_PRI : in std_logic;
R_n_recapture : in std_logic;
USER_R_n : in std_logic;
USER_W_n : in std_logic;
USER_BW_n : in std_logic_vector(3 downto 0);
USER_RESET : in std_logic;
USER_DATA_VALID : out std_logic;
QDR_Q : in std_logic_vector(data_bits-1 downto 0);
QDR_D : out std_logic_vector(data_bits-1 downto 0);
sys_rst180_val : out std_logic;
QDR_CQ : in std_logic;
QDR_CQ_n : in std_logic;
TEST_RESET_0 : out std_logic
);
end qdr2_burst_4_body;
architecture arc_qdr2_burst_4_body of qdr2_burst_4_body is
component FD
port( Q : out std_logic;
D : in std_logic;
C : in std_logic );
end component;
component data_path
port(
clk : in std_logic;
clk90 : in std_logic;
clk180 : in std_logic;
clk270 : in std_logic;
reset : in std_logic;
reset90 : in std_logic;
reset180 : in std_logic;
reset270 : in std_logic;
rst_cq_div : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
u_data_val : out std_logic;
qdr2_cq : in std_logic_vector(1 downto 0);
qdr2_q : in std_logic_vector(data_bits-1 downto 0);
user_output_data : out std_logic_vector (71 downto 0)
);
end component;
component IBUF_HSTL_II_18
port ( O : out std_logic;
I : in std_logic);
end component;
component OBUF_HSTL_II_18
port ( O : out std_logic;
I : in std_logic);
end component;
component FDS
port(Q:out std_logic;
D:in std_logic;
C:in std_logic;
S:in std_logic);
end component;
component write_burst_4
port ( D0 : in std_logic_vector (data_bits-1 downto 0);
D1 : in std_logic_vector (data_bits-1 downto 0);
CLK180 : in std_logic;
CLK90 : in std_logic;
CLK270 : in std_logic;
-- W_n : in std_logic;
RESET : in std_logic;
-- W_BAR : out std_logic;
Q : out std_logic_vector (data_bits-1 downto 0) );
end component;
component cal_top
port(
clk : in std_logic;
clk0 : in std_logic;
clk0dcmlock : in std_logic;
reset : in std_logic;
okToSelTap : in std_logic;
tapForDqs : out std_logic_vector( 4 downto 0)
);
end component;
signal CQ : std_logic_vector( 1 downto 0);
signal A_READ_FD : std_logic_vector(addr_bits-1 downto 0);
signal A_WRITE_FD : std_logic_vector(addr_bits -1 downto 0);
signal RESET : std_logic;
signal GND : std_logic;
signal HIGH : std_logic;
signal O_DDR_K_OBUF : std_logic;
signal O_DDR_K_n_OBUF : std_logic;
signal ReadInProgress : std_logic;
signal R_n_FD : std_logic;
signal W_BAR : std_logic;
signal R_BAR : std_logic;
signal D_data : std_logic_vector(data_bits-1 downto 0);
signal noReadCurrent : std_logic;
signal selTap : std_logic_vector( 4 downto 0);
signal QDR_R_n_ext_stage1 : std_logic;
signal QDR_R_n_ext_stage2 : std_logic;
signal QDR_R_n_ext_stage3 : std_logic;
signal MUX_ADDR : std_logic;
signal CalNoRead : std_logic;
signal ADR : std_logic_vector(addr_bits-1 downto 0);
signal sys_rst0_o : std_logic;
signal sys_rst0_1 : std_logic;
signal sys_rst0 : std_logic;
signal sys_rst90_o : std_logic;
signal sys_rst90_1 : std_logic;
signal sys_rst90 : std_logic;
signal sys_rst180_o : std_logic;
signal sys_rst180_1 : std_logic;
signal sys_rst180 : std_logic;
signal sys_rst270_o : std_logic;
signal sys_rst270_1 : std_logic;
signal sys_rst270 : std_logic;
signal QDR_R_n_ext_stage1_n: std_logic;
signal USER_DATA_VALID_val : std_logic;
signal USER_READ_E_val : std_logic;
signal USER_READ_E : std_logic;
signal USER_WRITE_E : std_logic;
begin
-- Signals assigment
GND <= '0' ;
HIGH <= '1';
USER_DATA_VALID <= USER_DATA_VALID_val;
noReadCurrent <= '1' WHEN USER_R_n ='1' and USER_DATA_VALID_val ='0' ELSE '0';
CQ <= ( QDR_CQ_n & QDR_CQ);
-- R_n_ext for synchronous scheme to generate pseudo valid data signal
RESET <= USER_RESET;
TEST_RESET_0 <= sys_rst0;
sys_rst180_val <=sys_rst180;
-- Generation of the reset signal in the different clock domains
process (CLK0E)
begin
if CLK0E'event and CLK0E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst0_o <= '1';
sys_rst0_1 <= '1';
sys_rst0 <= '1';
else
sys_rst0_o <= '0';
sys_rst0_1 <= sys_rst0_o;
sys_rst0 <= sys_rst0_1;
end if;
end if;
end process;
process (CLK90E)
begin
if CLK90E'event and CLK90E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst90_o <= '1';
sys_rst90_1 <= '1';
sys_rst90 <= '1';
else
sys_rst90_o <= '0';
sys_rst90_1 <= sys_rst90_o;
sys_rst90 <= sys_rst90_1;
end if;
end if;
end process;
process (CLK180E)
begin
if CLK180E'event and CLK180E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst180_o <= '1';
sys_rst180_1 <= '1';
sys_rst180 <= '1';
else
sys_rst180_o <= '0';
sys_rst180_1 <= sys_rst180_o;
sys_rst180 <= sys_rst180_1;
end if;
end if;
end process;
process (CLK270E)
begin
if CLK270E'event and CLK270E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst270_o <= '1';
sys_rst270_1 <= '1';
sys_rst270 <= '1';
else
sys_rst270_o <= '0';
sys_rst270_1 <= sys_rst270_o;
sys_rst270 <= sys_rst270_1;
end if;
end if;
end process;
-- Write data bus to QDR II SRAM device
g3 : for i3 in 0 to data_bits-1 generate
INST_QDR_OBUF_DWRITE : OBUF_HSTL_II_18 port map (I => D_data(i3) , O => QDR_D(i3) );
end generate;
-- Write operation module
-- RAKCHOPR -- Added reset port
INST_Write : write_burst_4 port map (CLK90 => CLK90E,
CLK270 => CLK270E,
D0 => USER_DWH,
D1 => USER_DWL ,
-- W_n => USER_W_n ,
-- W_BAR => W_BAR ,
Q => D_data ,
CLK180 => CLK180E ,
RESET => RESET
);
--*****************************************************************************************
-- Calibration circuit
--*****************************************************************************************
FD_NoRead : FD port map (Q => CalNoRead ,
D => noReadCurrent ,
C => CLK0E );
--CalNoRead out of CLK0 enables tap change from the calibration circuit when there is no read current
cal_inst : cal_top port map (clk => CLK_BUF,
clk0 => CLK0E,
clk0dcmlock => LOCKED_DCM_PRI,
reset => sys_rst0,
okToSelTap => CalNoRead,
tapForDqs => selTap
);
-- Read datapath implementation
Read_data_path : data_path
port map( clk => CLK0E,
clk90 => CLK90E,
clk180 => CLK180E,
clk270 => CLK270E,
reset => sys_rst0,
reset90 => sys_rst90,
reset180 => sys_rst180,
reset270 => sys_rst270,
rst_cq_div => R_n_recapture,
delay_sel => selTap,
u_data_val => USER_DATA_VALID_val,
qdr2_cq => CQ,
qdr2_q => QDR_Q,
user_output_data=> USER_Q
);
end arc_qdr2_burst_4_body;
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