📄 data_path.vhd
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CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(15),
fbit_1 => fbit_1(15),
fbit_2 => fbit_2(15),
fbit_3 => fbit_3(15)
);
qdr2_qbit_16 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(16),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(16),
fbit_1 => fbit_1(16),
fbit_2 => fbit_2(16),
fbit_3 => fbit_3(16)
);
qdr2_qbit_17 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(17),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(17),
fbit_1 => fbit_1(17),
fbit_2 => fbit_2(17),
fbit_3 => fbit_3(17)
);
qdr2_qbit_bar_0 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(18),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(18),
fbit_1 => fbit_1(18),
fbit_2 => fbit_2(18),
fbit_3 => fbit_3(18)
);
qdr2_qbit_bar_1 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(19),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(19),
fbit_1 => fbit_1(19),
fbit_2 => fbit_2(19),
fbit_3 => fbit_3(19)
);
qdr2_qbit_bar_2 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(20),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(20),
fbit_1 => fbit_1(20),
fbit_2 => fbit_2(20),
fbit_3 => fbit_3(20)
);
qdr2_qbit_bar_3 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(21),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(21),
fbit_1 => fbit_1(21),
fbit_2 => fbit_2(21),
fbit_3 => fbit_3(21)
);
qdr2_qbit_bar_4 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(22),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(22),
fbit_1 => fbit_1(22),
fbit_2 => fbit_2(22),
fbit_3 => fbit_3(22)
);
qdr2_qbit_bar_5 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(23),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(23),
fbit_1 => fbit_1(23),
fbit_2 => fbit_2(23),
fbit_3 => fbit_3(23)
);
qdr2_qbit_bar_6 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(24),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(24),
fbit_1 => fbit_1(24),
fbit_2 => fbit_2(24),
fbit_3 => fbit_3(24)
);
qdr2_qbit_bar_7 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(25),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(25),
fbit_1 => fbit_1(25),
fbit_2 => fbit_2(25),
fbit_3 => fbit_3(25)
);
qdr2_qbit_bar_8 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(26),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(26),
fbit_1 => fbit_1(26),
fbit_2 => fbit_2(26),
fbit_3 => fbit_3(26)
);
qdr2_qbit_bar_9 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(27),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(27),
fbit_1 => fbit_1(27),
fbit_2 => fbit_2(27),
fbit_3 => fbit_3(27)
);
qdr2_qbit_bar_10 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(28),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(28),
fbit_1 => fbit_1(28),
fbit_2 => fbit_2(28),
fbit_3 => fbit_3(28)
);
qdr2_qbit_bar_11 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(29),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(29),
fbit_1 => fbit_1(29),
fbit_2 => fbit_2(29),
fbit_3 => fbit_3(29)
);
qdr2_qbit_bar_12 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(30),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(30),
fbit_1 => fbit_1(30),
fbit_2 => fbit_2(30),
fbit_3 => fbit_3(30)
);
qdr2_qbit_bar_13 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(31),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(31),
fbit_1 => fbit_1(31),
fbit_2 => fbit_2(31),
fbit_3 => fbit_3(31)
);
qdr2_qbit_bar_14 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(32),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(32),
fbit_1 => fbit_1(32),
fbit_2 => fbit_2(32),
fbit_3 => fbit_3(32)
);
qdr2_qbit_bar_15 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(33),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(33),
fbit_1 => fbit_1(33),
fbit_2 => fbit_2(33),
fbit_3 => fbit_3(33)
);
qdr2_qbit_bar_16 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(34),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(34),
fbit_1 => fbit_1(34),
fbit_2 => fbit_2(34),
fbit_3 => fbit_3(34)
);
qdr2_qbit_bar_17 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(35),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(35),
fbit_1 => fbit_1(35),
fbit_2 => fbit_2(35),
fbit_3 => fbit_3(35)
);
--****************************************************************************************************************************
RAM_18D_cq0_fbit0 : RAM_18D port map (
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_00,
D => fbit_0(17 downto 0),
DPO => fifo_00_data_out );
RAM_18D_cq0_fbit1 : RAM_18D port map (
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_01,
D => fbit_1(17 downto 0),
DPO => fifo_01_data_out );
RAM_18D_cq0_fbit2 : RAM_18D port map (
A0 => fifo_02_wr_addr(0),
A1 => fifo_02_wr_addr(1),
A2 => fifo_02_wr_addr(2),
A3 => fifo_02_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_02,
D => fbit_2(17 downto 0),
DPO => fifo_02_data_out );
RAM_18D_cq0_fbit3 : RAM_18D port map (
A0 => fifo_03_wr_addr(0),
A1 => fifo_03_wr_addr(1),
A2 => fifo_03_wr_addr(2),
A3 => fifo_03_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_03,
D => fbit_3(17 downto 0),
DPO => fifo_03_data_out );
RAM_18D_cq1_fbit0 : RAM_18D port map (
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_10,
D => fbit_0(35 downto 18),
DPO => fifo_10_data_out );
RAM_18D_cq1_fbit1 : RAM_18D port map (
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_11,
D => fbit_1(35 downto 18),
DPO => fifo_11_data_out );
RAM_18D_cq1_fbit2 : RAM_18D port map (
A0 => fifo_12_wr_addr(0),
A1 => fifo_12_wr_addr(1),
A2 => fifo_12_wr_addr(2),
A3 => fifo_12_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_12,
D => fbit_2(35 downto 18),
DPO => fifo_12_data_out );
RAM_18D_cq1_fbit3 : RAM_18D port map (
A0 => fifo_13_wr_addr(0),
A1 => fifo_13_wr_addr(1),
A2 => fifo_13_wr_addr(2),
A3 => fifo_13_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_13,
D => fbit_3(35 downto 18),
DPO => fifo_13_data_out );
end arc_data_path;
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