data_path.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright =>C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR=>tm) SRAM Virtex=>tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
--**
--**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
--**              provided to you "as is". Xilinx and its licensors make and you 
--**              receive no warranties or conditions, express, implied, statutory 
--**              or otherwise, and Xilinx specifically disclaims any implied 
--**              warranties of merchantability, non-infringement, or fitness for a 
--**              particular purpose. Xilinx does not warrant that the functions 
--**              contained in these designs will meet your requirements, or that the
--**              operation of these designs will be uninterrupted or error free, or 
--**              that defects in the Designs will be corrected. Furthermore, Xilinx 
--**              does not warrant or make any representations regarding use or the 
--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
--**
--**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
--**              liable for any loss of data, lost profits, cost or procurement of 
--**              substitute goods or services, or for any special, incidental, 
--**              consequential, or indirect damages arising from the use or operation 
--**              of the designs or accompanying documentation, however caused and on 
--**              any theory of liability. This limitation will apply even if Xilinx 
--**              has been advised of the possibility of such damage. This limitation 
--**              shall apply not-withstanding the failure of the essential purpose of 
--**              any limited remedies herein. 
--**
--*****************************************************************************************
--*****************************************************************************************
--**
--**  www.xilinx.com               Copyright =>c) 1984-2004 Xilinx, Inc. All rights reserved
--** 
--**  QDR=>tm)-II SRAM Virtex=>tm)-II Interface                         Verilog instanciation
--**
--*****************************************************************************************
--**
--**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
--**              provided to you \"as is\". Xilinx and its licensors make and you 
--**              receive no warranties or conditions, express, implied, statutory 
--**              or otherwise, and Xilinx specifically disclaims any implied 
--**              warranties of merchantability, non-infringement, or fitness for a 
--**              particular purpose. Xilinx does not warrant that the functions 
--**              contained in these designs will meet your requirements, or that the
--**              operation of these designs will be uninterrupted or error free, or 
--**              that defects in the Designs will be corrected. Furthermore, Xilinx 
--**              does not warrant or make any representations regarding use or the 
--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
--**
--**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
--**              liable for any loss of data, lost profits, cost or procurement of 
--**              substitute goods or services, or for any special, incidental, 
--**              consequential, or indirect damages arising from the use or operation 
--**              of the designs or accompanying documentation, however caused and on 
--**              any theory of liability. This limitation will apply even if Xilinx 
--**              has been advised of the possibility of such damage. This limitation 
--**              shall apply not-withstanding the failure of the essential purpose of 
--**              any limited remedies herein. 
--**
--*****************************************************************************************
-- Description :     This module comprises read data paths for the qdr2 memory interface.                 
--                   The read data is captured in CLB FFs and finally input to FIFOs.
--                     
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity data_path is

generic (
   -- Constant Parameters
   addr_bits : INTEGER :=     18;
   data_bits : INTEGER :=     36;
   mem_sizes : INTEGER := 524287
   );

port(
	         clk		  : in std_logic;
	         clk90		  : in std_logic;
	         clk180		 : in std_logic;
	         clk270   : in std_logic;
	         reset		  : in std_logic;
	         reset90		: in std_logic;
	         reset180	: in std_logic;
	         reset270	: in std_logic;
	         rst_cq_div	 : in std_logic;
	         delay_sel	  : in std_logic_vector (4 downto 0);	
	         u_data_val	 : out std_logic;
	         qdr2_cq		   : in std_logic_vector (1 downto 0);
	         qdr2_q		    : in std_logic_vector (data_bits-1 downto 0);
	         user_output_data : out std_logic_vector (71 downto 0)
--	         ;TEST_CAPTURE_D0  : out std_logic
                 );

end data_path;
   
architecture arc_data_path of data_path is                  
   
component RAM_18D
port ( A0 : in std_logic;
       A1 : in std_logic;
       A2 : in std_logic;
       A3 : in std_logic;
       DPRA0 : in std_logic;
       DPRA1 : in std_logic;
       DPRA2 : in std_logic;
       DPRA3 : in std_logic;
       WCLK  : in std_logic;
       WE    : in std_logic;
       D     : in std_logic_vector (addr_bits-1 downto 0);
       DPO   : out std_logic_vector (addr_bits-1 downto 0) );
end component;

component cq_delay
port ( clk_in  : in std_logic;
       sel_in  : in std_logic_vector (4 downto 0);
       clk_out : out std_logic );
end component;

component qdr2_cq_div
port ( cq 			: in std_logic;
       cq1 			: in std_logic;
       rst_cq_div 			: in std_logic;
       cq_tranfert_col0 : out std_logic;
       cq_tranfert_col1 : out std_logic );
end component;

component qdr2_cq_bar_div
port ( cq 			: in std_logic;
       cq1 			: in std_logic;
       rst_cq_div 	     : in std_logic;
       cq_tranfert_col0 : out std_logic;
       cq_tranfert_col1 : out std_logic );
end component;

component qdr2_transfer_done
port ( clk0 		: in std_logic;
       clk90 		: in std_logic;
       clk180 		: in std_logic;
       clk270 		: in std_logic;              
       reset 		: in std_logic;
       reset90 	: in std_logic;
       reset180 : in std_logic;
       reset270 : in std_logic;
       cq_div 		: in std_logic;
       transfer_done0 	: out std_logic;
       transfer_done1 	: out std_logic;
       transfer_done2 	: out std_logic;
       transfer_done3 	: out std_logic );
end component;

component v2p_qdr2_input_buffer
 port ( qdr2_in 		   : in std_logic;
        read_data_in : out std_logic );
end component;

component qdr_q_iob
port ( qdr_q   : in std_logic_vector (data_bits-1 downto 0);
       qdr_q_i : out std_logic_vector (data_bits-1 downto 0) );
end component;
   
component qdr2_qbit_cq
port ( reset 	: in std_logic;
       cq 		: in std_logic;
       cq1 		: in std_logic;
       qdr2_q 	: in std_logic;
       CE_R_FB0 	: in std_logic;
       CE_R_FB1 	: in std_logic;
       CE_R_FB2 	: in std_logic;
       CE_R_FB3 	: in std_logic;
       fbit_0 	: out std_logic;
       fbit_1 	: out std_logic;
       fbit_2 	: out std_logic;
       fbit_3 	: out std_logic );
end component;

component qdr2_qbit_cq_bar
port ( reset    : in std_logic;
       cq 	    : in std_logic;
       cq1 	    : in std_logic;
       qdr2_q   : in std_logic;
       CE_R_FB0 : in std_logic;
       CE_R_FB1 : in std_logic;
       CE_R_FB2 : in std_logic;
       CE_R_FB3 : in std_logic;
       fbit_0   : out std_logic;
       fbit_1   : out std_logic;
       fbit_2   : out std_logic;
       fbit_3   : out std_logic );
end component;
   
signal cq_int_delay_in0: std_logic;
signal cq_int_delay_in1: std_logic;

signal cq_delayed_col0: std_logic_vector (1 downto 0); -- delayed strobe
signal cq_delayed_col1: std_logic_vector (1 downto 0); -- delayed strobe

signal cq_div_transfert_0_col0: std_logic;
signal cq_div_transfert_0_col1: std_logic;
signal cq_div_transfert_1_col0: std_logic;
signal cq_div_transfert_1_col1: std_logic;

signal transfer_done_00: std_logic;
signal transfer_done_01: std_logic;
signal transfer_done_02: std_logic;
signal transfer_done_03: std_logic;
signal transfer_done_10: std_logic;
signal transfer_done_11: std_logic;
signal transfer_done_12: std_logic;
signal transfer_done_13: std_logic;

signal fbit_0: std_logic_vector (data_bits-1 downto 0);
signal fbit_1: std_logic_vector (data_bits-1 downto 0);
signal fbit_2: std_logic_vector (data_bits-1 downto 0);
signal fbit_3: std_logic_vector (data_bits-1 downto 0);

signal fifo_00_data_out: std_logic_vector (addr_bits-1 downto 0);
signal fifo_01_data_out: std_logic_vector (addr_bits-1 downto 0);     
signal fifo_02_data_out: std_logic_vector (addr_bits-1 downto 0);     
signal fifo_03_data_out: std_logic_vector (addr_bits-1 downto 0);      

signal fifo_10_data_out: std_logic_vector (addr_bits-1 downto 0);
signal fifo_11_data_out: std_logic_vector (addr_bits-1 downto 0);     
signal fifo_12_data_out: std_logic_vector (addr_bits-1 downto 0);     
signal fifo_13_data_out: std_logic_vector (addr_bits-1 downto 0);     

signal fifo_00_wr_addr: std_logic_vector (3 downto 0);
signal fifo_01_wr_addr: std_logic_vector (3 downto 0);
signal fifo_02_wr_addr: std_logic_vector (3 downto 0);
signal fifo_03_wr_addr: std_logic_vector (3 downto 0);

signal fifo_00_rd_addr: std_logic_vector (3 downto 0);
signal fifo_02_rd_addr: std_logic_vector (3 downto 0);

signal fifo_10_wr_addr: std_logic_vector (3 downto 0);
signal fifo_11_wr_addr: std_logic_vector (3 downto 0);
signal fifo_12_wr_addr: std_logic_vector (3 downto 0);
signal fifo_13_wr_addr: std_logic_vector (3 downto 0);

signal fifo_11_not_empty: std_logic;
signal fifo_13_not_empty: std_logic;

signal fifo_11_not_empty_r: std_logic;
signal fifo_13_not_empty_r: std_logic;

signal read_valid_data_1: std_logic;
signal read_valid_data_2: std_logic;
signal read_valid_data: std_logic;
signal rd_data_valid: std_logic;
signal next_state: std_logic;

signal reset_r: std_logic;
signal reset90_r: std_logic;
signal reset180_r: std_logic;
signal reset270_r: std_logic;
signal rst_cq_div_int: std_logic;
signal rst_cq_div_reg_fd1: std_logic;

signal CE_R_FB0: std_logic;
signal CE_R_FB1: std_logic;
signal CE_R_FB2: std_logic;
signal CE_R_FB3: std_logic;

signal cq_delayed_col0_0_inv : std_logic;

begin
read_valid_data_1 <= '1' WHEN  (fifo_11_not_empty_r = '1' and fifo_11_not_empty = '1') ELSE '0';

read_valid_data_2 <= '1' WHEN  fifo_13_not_empty_r = '1' and fifo_13_not_empty = '1' ELSE '0';

read_valid_data <= read_valid_data_1 or read_valid_data_2;

u_data_val <= rd_data_valid;

--TEST_CAPTURE_D0 <= fbit_0(0);

fifo_11_not_empty <= '0' WHEN ( fifo_00_rd_addr(3 downto 0) = fifo_11_wr_addr(3 downto 0) ) ELSE '1';

fifo_13_not_empty <= '0' WHEN ( fifo_02_rd_addr(3 downto 0) = fifo_13_wr_addr(3 downto 0) ) ELSE '1';


-- Write Address incrementation for the read FIFO

process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_00_wr_addr <=  "0000";
   elsif transfer_done_00 = '1' then
      fifo_00_wr_addr <= fifo_00_wr_addr + "0001";
   end if;
 end if;
end process;
   	  
process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_01_wr_addr <=  "0000";
   elsif transfer_done_01 = '1' then
      fifo_01_wr_addr <= fifo_01_wr_addr + "0001";
   end if;
 end if;
end process;

process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_02_wr_addr <=  "0000";
   elsif transfer_done_02 = '1' then
      fifo_02_wr_addr <= fifo_02_wr_addr + "0001";
   end if;
 end if;
end process;

process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_03_wr_addr <=  "0000";
   elsif transfer_done_03 = '1' then
      fifo_03_wr_addr <= fifo_03_wr_addr + "0001";
   end if;
 end if;
end process;

process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_10_wr_addr <=  "0000";
   elsif transfer_done_10 = '1' then
      fifo_10_wr_addr <= fifo_10_wr_addr + "0001";
   end if;
 end if;
end process;
   	  
process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_11_wr_addr <=  "0000";
   elsif transfer_done_11 = '1' then
      fifo_11_wr_addr <= fifo_11_wr_addr + "0001";
   end if;
 end if;
end process;

process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_12_wr_addr <=  "0000";
   elsif transfer_done_12 = '1' then
      fifo_12_wr_addr <= fifo_12_wr_addr +"0001";
   end if;
 end if;
end process;

process (clk90)
begin
 if clk90'event and clk90 = '1' then
    if reset90_r ='1' then
    	  fifo_13_wr_addr <=  "0000";
   elsif transfer_done_13 = '1' then
      fifo_13_wr_addr <= fifo_13_wr_addr + "0001";
   end if;
 end if;
end process;

  user_output_reg : PROCESS
  BEGIN
    WAIT UNTIL clk90'event and clk90 = '1';
      IF (reset90_r = '1')  THEN
               next_state <= '0';
               fifo_00_rd_addr <= "0000";
               fifo_02_rd_addr <= "0000";
               user_output_data <= (others => '0'); 
      ELSE
        CASE next_state is
          WHEN '0' =>
            IF (read_valid_data_1 = '1') THEN
               next_state <= '1';
               fifo_00_rd_addr <= fifo_00_rd_addr + "0001";
               user_output_data <= (fifo_10_data_out & fifo_00_data_out & fifo_11_data_out & fifo_01_data_out); 
            ELSE 
              next_state <= '0';
            END IF;

          WHEN '1' =>
            IF (read_valid_data_2 = '1') THEN
               next_state <= '0';
               fifo_02_rd_addr <= fifo_02_rd_addr + "0001";
               user_output_data <= (fifo_12_data_out & fifo_02_data_out & fifo_13_data_out & fifo_03_data_out); 
            ELSE
               next_state <= '1';
            END IF;