write_burst_4.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--**
--**  www.xilinx.com                   Copyright (C) 2003 Xilinx, Inc.  All rights reserved
--**  
--**  QDR(tm) SRAM Virtex(tm)-II Interface                               VHDL instanciation
--**
--*****************************************************************************************
--**
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--**              contained in these designs will meet your requirements, or that the
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--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
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--*****************************************************************************************

--***********************************************
--* Library declaration
--***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--pragma translate_off
--synopsys translate_off
 LIBRARY UNISIM;
 use UNISIM.VCOMPONENTS.ALL;
--synopsys translate_on
--pragma translate_on

entity write_burst_4 is

generic (
   -- Constant Parameters
   addr_bits : INTEGER :=     18;
   data_bits : INTEGER :=     18;
   mem_sizes : INTEGER := 524287
   );

port ( D0 : in std_logic_vector (data_bits-1 downto 0);
       D1 : in std_logic_vector (data_bits-1 downto 0);
       CLK180 : in std_logic;
       CLK90 : in std_logic;
       CLK270 : in std_logic;
       W_n : in std_logic;
       RESET : in std_logic;
       W_BAR : out std_logic;
       Q : out std_logic_vector (data_bits-1 downto 0) );

end write_burst_4;

architecture write_burst_4_arch of write_burst_4 is

--***********************************************
--* Components declaration
--***********************************************

component FD
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic );
end component;

component FDDRRSE
  port( Q : out std_logic;
        D0 : in std_logic; 
        D1 : in std_logic;
        C0 : in std_logic;
        C1 : in std_logic;
        CE : in std_logic;
        R : in std_logic;
        S : in std_logic );
end component;

--***********************************************
--* Signals and constants declaration
--***********************************************

attribute syn_keep : boolean;
 signal D0_S1 : std_logic_vector (data_bits-1 downto 0);
 signal D0_S2 : std_logic_vector (data_bits-1 downto 0);
 signal D1_S1 : std_logic_vector (data_bits-1 downto 0);
 signal D1_S2 : std_logic_vector (data_bits-1 downto 0);
 signal D0_Initial : std_logic_vector (data_bits-1 downto 0);
 signal W_n_1 : std_logic;
 signal W_n_2 : std_logic;
 signal GND : std_logic := '0';
 signal HIGH : std_logic := '1';


begin


INST_WRITE : for I in (data_bits - 1) downto 0 generate 

 WRT_FDC_D0_initial : FD port map (
                         Q => D0_Initial(i),
                         D => D0(i),
                         C => CLK180 );

 WRT_FDC_D1_S1 : FD port map (
                         Q => D1_S1(i),
                         D => D1(i),
                         C => CLK270 );

 WRT_FDC_D0_S1 : FD port map (
                         Q => D0_S1(i),
                         D => D0_Initial(i),
                         C => CLK90 );

 WRT_FDC_D1_S2 : FD port map (
                         Q => D1_S2(i),
                         D => D1_S1(i),
                         C => CLK270 );

 WRT_FDC_D0_S2 : FD port map (
                         Q => D0_S2(i),
                         D => D0_S1(i),
                         C => CLK90 );

 WRT_FDDR_DQ : FDDRRSE port map (
                        Q => Q(i),
                        D0 => D0_S2(i),
                        D1 => D1_S2(i),
                        C0 => CLK90,
                        C1 => CLK270,
                        CE => HIGH,
                        R => GND,
                        S => GND );
end generate;

 WRT_PIPE : FD port map (
                         Q => W_n_1,
                         D => W_n,
                         C => CLK270 );

 WRT_FD_W_n : FDDRRSE port map (
                        Q => W_BAR,
                        D0 => W_n_1,
                        D1 => HIGH,
                        C0 => CLK270,
                        C1 => CLK90,
                        CE => HIGH,
                        R => GND,
                        S => RESET );

end write_burst_4_arch;