qdr2_burst_4_body.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

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 --** 
 --**  www.xilinx.com               Copyright c) 1984-2004 Xilinx, Inc. All rights reserved
 --** 
 --**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         VHDL instanciation
 --**
 --*****************************************************************************************
 --**
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 --**              contained in these designs will meet your requirements, or that the
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 -- This module is the top level architecture for the memory interface design.
 -- The signals connections are describled in the application note. 
 -- The ports naming convention is as follows:
 -- - user side: USER_INSTNAME
 -- - memory side: QDR_INSTNAME

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity qdr2_burst_4_body is 

generic (
   -- Constant Parameters
   addr_bits : INTEGER :=     18;
   data_bits : INTEGER :=     18;
   mem_sizes : INTEGER := 524287
   );

port (	USER_DWL 		: in std_logic_vector(data_bits-1 downto 0);
        USER_DWH 			: in std_logic_vector(data_bits-1 downto 0);
        USER_Q		 	: out std_logic_vector(35 downto 0);
        USER_A_READ 		: in std_logic_vector(addr_bits-1 downto 0);
        USER_A_WRITE 		: in std_logic_vector(addr_bits-1 downto 0);
        CLK_BUF			: in std_logic;
        CLK0E			: in std_logic;
        CLK90E			: in std_logic;
        CLK180E			: in std_logic;
        CLK270E			: in std_logic;
        LOCKED_DCM_PRI		: in std_logic;
        USER_R_n			: in std_logic;
        USER_W_n			: in std_logic;
        USER_BW_n			: in std_logic_vector(1 downto 0);
        USER_RESET		: in std_logic;
        USER_DATA_VALID		: out std_logic;
        QDR_Q			: in std_logic_vector(data_bits-1 downto 0);
        QDR_D			: out std_logic_vector(data_bits-1 downto 0);
        QDR_SA			: out std_logic_vector(addr_bits-1 downto 0);
        QDR_R_n			: out std_logic;
        QDR_W_n			: out std_logic;
        QDR_BW_n			: out std_logic_vector(1 downto 0);
        QDR_K			: out std_logic;
        QDR_K_n			: out std_logic;
        QDR_C			: out std_logic;
        QDR_C_n			: out std_logic;
        QDR_CQ			: in std_logic;
        QDR_CQ_n			: in std_logic;
        QDR_R_n_ext		: out std_logic;
        QDR_R_n_int		: in std_logic;
        TEST_RESET_0		: out std_logic
        );
end qdr2_burst_4_body;

architecture arc_qdr2_burst_4_body of qdr2_burst_4_body is
component FD
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic );
end component;

component FDDRRSE
  port( Q 	: out std_logic;
        D0 : in std_logic; 
        D1 : in std_logic;
        C0 : in std_logic;
        C1 : in std_logic;
        CE : in std_logic;
        R 	: in std_logic;
        S 	: in std_logic );
end component;

component data_path
port(
        clk				: in std_logic;
        clk90			: in std_logic;
        clk180			: in std_logic;
        clk270   			: in std_logic;
        reset			: in std_logic;
        reset90			: in std_logic;
        reset180			: in std_logic;
        reset270			: in std_logic;
        rst_cq_div		: in std_logic;
        delay_sel			: in std_logic_vector(4 downto 0);
        u_data_val		: out std_logic;
        qdr2_cq			: in std_logic_vector(1 downto 0);
        qdr2_q			: in std_logic_vector(data_bits-1 downto 0);
        user_output_data	: out std_logic_vector (35 downto 0)
        );
end component;

component IBUF_HSTL_II_18 
port (	O	: out std_logic;
	I	: in std_logic);    
end component;   

component OBUF_HSTL_II_18 
port (	O	: out std_logic;
	I	: in std_logic);    
end component;   

component FDS 
port(Q:out std_logic;
     D:in std_logic;
     C:in std_logic;
     S:in std_logic);
end component;
     
component write_burst_4 

port ( D0 		: in std_logic_vector (data_bits-1 downto 0);
       D1 		: in std_logic_vector (data_bits-1 downto 0);
       CLK180 	: in std_logic;
       CLK90 	: in std_logic;
       CLK270	: in std_logic;
       W_n 		: in std_logic;
       RESET 	: in std_logic;
       W_BAR 	: out std_logic;
       Q 		: out std_logic_vector (data_bits-1 downto 0) );
end component;

component cal_top 
port(
     clk         : in std_logic;
     clk0        : in std_logic;
     clk0dcmlock : in std_logic;
     reset       : in std_logic;
     okToSelTap  : in std_logic;
     tapForDqs   : out std_logic_vector( 4 downto 0)
     );
end component;

component qdr2_fsm_access 
port ( CLK 		: in std_logic;
       RESET 	: in std_logic;
       USER_W_n 	: in std_logic;
       USER_R_n 	: in std_logic;
       WRITE_E 	: out std_logic;
       READ_E 	: out std_logic;
       CLK_A_RD 	: in std_logic;
       MUX_ADR_RD : out std_logic );
end component;

signal CQ 			: std_logic_vector( 1 downto 0);
signal A_READ_FD			: std_logic_vector(addr_bits-1 downto 0);
signal A_WRITE_FD			: std_logic_vector(addr_bits -1 downto 0);
signal RESET  			: std_logic;                                                      
signal GND  			: std_logic;                                                        
signal HIGH  			: std_logic;                                                                                                                                                            
signal O_DDR_K_OBUF  			: std_logic;
signal O_DDR_K_n_OBUF  	: std_logic;                                 
signal ReadInProgress  	: std_logic;                                  
signal R_n_FD  			: std_logic;                                                      
signal W_BAR  			: std_logic;
signal R_BAR  			: std_logic;                                               
signal D_data  			: std_logic_vector(data_bits-1 downto 0); 
signal noReadCurrent  		: std_logic;
signal selTap  			: std_logic_vector( 4 downto 0);
signal QDR_R_n_ext_stage1  : std_logic;
signal QDR_R_n_ext_stage2  : std_logic;
signal QDR_R_n_ext_stage3  : std_logic;
signal R_n_recapture  		: std_logic;
signal MUX_ADDR  			: std_logic;
signal CalNoRead  			: std_logic;
signal ADR  			: std_logic_vector(addr_bits-1 downto 0);	
signal sys_rst0_o  			: std_logic; 
signal sys_rst0_1  			: std_logic; 
signal sys_rst0  			: std_logic;   
signal sys_rst90_o  			: std_logic;
signal sys_rst90_1  			: std_logic;
signal sys_rst90  			: std_logic;
signal sys_rst180_o  			: std_logic;
signal sys_rst180_1  			: std_logic;
signal sys_rst180  			: std_logic;
signal sys_rst270_o  			: std_logic;
signal sys_rst270_1  			: std_logic;
signal sys_rst270  			: std_logic;
signal QDR_R_n_ext_stage1_n: std_logic;
signal USER_DATA_VALID_val : std_logic;
signal USER_READ_E_val     : std_logic;
signal USER_READ_E     : std_logic;
signal USER_WRITE_E     : std_logic;

begin	
 -- Signals assigment                                                                                     

GND <= '0' ;                                               
HIGH <= '1';                          
USER_DATA_VALID <= USER_DATA_VALID_val;