qdr_lc_top.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--** 
--**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
--** 
--**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         VHDL instanciation
--**
--*****************************************************************************************
--**
--**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
--**              provided to you "as is". Xilinx and its licensors make and you 
--**              receive no warranties or conditions, express, implied, statutory 
--**              or otherwise, and Xilinx specifically disclaims any implied 
--**              warranties of merchantability, non-infringement, or fitness for a 
--**              particular purpose. Xilinx does not warrant that the functions 
--**              contained in these designs will meet your requirements, or that the
--**              operation of these designs will be uninterrupted or error free, or 
--**              that defects in the Designs will be corrected. Furthermore, Xilinx 
--**              does not warrant or make any representations regarding use or the 
--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
--**
--**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
--**              liable for any loss of data, lost profits, cost or procurement of 
--**              substitute goods or services, or for any special, incidental, 
--**              consequential, or indirect damages arising from the use or operation 
--**              of the designs or accompanying documentation, however caused and on 
--**              any theory of liability. This limitation will apply even if Xilinx 
--**              has been advised of the possibility of such damage. This limitation 
--**              shall apply not-withstanding the failure of the essential purpose of 
--**              any limited remedies herein. 
--**
--*****************************************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity QDR_LC_TOP is 
generic (
   -- Constant Parameters
	addr_bits 		: INTEGER := 18;
	data_bits 		: INTEGER := 18);
	
port(   CLK200 	     		: in std_logic;
	CLK200N	     	: in std_logic; 
	Reset       		: in std_logic; 
	
        GCLK0_val			: out std_logic; 
	GCLK90_val		: out std_logic; 
        GCLK180_val			: out std_logic; 
	GCLK270_val		: out std_logic; 	
	Reset_CLK0		: out std_logic; 
	DataR		: out std_logic_vector (35 downto 0); 
	UserDataValid		: out std_logic; 
	DCM_LOCKED_val		: out std_logic; 
	R_n_recapture   : in std_logic; 
	sys_rst180      : out std_logic; 
	Cout_WDataL		: in std_logic_vector (data_bits-1 downto 0); 
	Cout_WDataH		: in std_logic_vector (data_bits-1 downto 0);  
	R_n		: in std_logic;
	W_n		: in std_logic;
	mem_D 	     	: out std_logic_vector (data_bits-1 downto 0); 
	mem_Q	     	: in std_logic_vector  (data_bits-1 downto 0); 
	mem_CQ	     	: in std_logic; 
	mem_CQ_n	   	: in std_logic
);
		  
	
end QDR_LC_TOP;



architecture arc_QDR_LC_TOP of QDR_LC_TOP is 


component FD
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic );
end component;

component  qdr2_burst_4_body 
port (	USER_DWL 		: in std_logic_vector(data_bits-1 downto 0);
        USER_DWH 			: in std_logic_vector(data_bits-1 downto 0);
        USER_Q		 	: out std_logic_vector(35 downto 0);
        CLK_BUF			: in std_logic;
        CLK0E			: in std_logic;
        CLK90E			: in std_logic;
        CLK180E			: in std_logic;
        CLK270E			: in std_logic;
        LOCKED_DCM_PRI		: in std_logic;
        R_n_recapture   : in std_logic;        
        USER_R_n			: in std_logic;
        USER_W_n			: in std_logic;
        USER_BW_n			: in std_logic_vector(1 downto 0);
        USER_RESET			: in std_logic;
        USER_DATA_VALID	: out std_logic;
        QDR_Q			: in std_logic_vector(data_bits-1 downto 0);
        QDR_D			: out std_logic_vector(data_bits-1 downto 0);
        sys_rst180_val  : out std_logic;
        QDR_CQ			: in std_logic;
        QDR_CQ_n			: in std_logic;
        TEST_RESET_0			: out std_logic
        );
end component;

component QDR2_RESET
port( ML365_RESET : in std_logic ;
      USER_RESET  : out std_logic);
end component;

component qdr2_clocks
 port ( 		USER_CLK 		: in std_logic;
		USER_CLK_N 		: in std_logic;
		RESET 		: in std_logic;
        		CLK_BUF 		: out std_logic;
		GCLK0 		: out std_logic;
        		GCLK90 		: out std_logic;
		GCLK180 		: out std_logic;
        		GCLK270 		: out std_logic;
            		CLKDIV2		: out std_logic;
            		LOCKED_DCM 		: out std_logic );

end component;

--*****************************************************************************************
-- Signal between qdr2_clocks qdr2_burst_4_body
--*****************************************************************************************

signal CLK_BUF 		: std_logic ;
signal GCLK0 		 : std_logic ;
signal GCLK90 		 : std_logic ;
signal GCLK180   : std_logic ;
signal GCLK270   : std_logic ;
signal CLK_DIV2  : std_logic ;
signal DCM_LOCKED: std_logic ;

signal DCM_LOCKED_n 				: std_logic;   
signal USER_RESET 				: std_logic;  

signal GCLK0_val1               : std_logic; 
signal GCLK0_val2               : std_logic; 

signal GCLK90_val1               : std_logic; 
signal GCLK90_val2               : std_logic; 

signal GCLK180_val1               : std_logic; 
signal GCLK180_val2               : std_logic; 

signal GCLK270_val1               : std_logic; 
signal GCLK270_val2               : std_logic; 

begin 
DCM_LOCKED_n 		<= not DCM_LOCKED;
GCLK0_val 		<= GCLK0;
GCLK90_val 		<= GCLK90;
GCLK180_val 		<= GCLK180;
GCLK270_val 		<= GCLK270;

DCM_LOCKED_val  <= DCM_LOCKED;

GCLK0_val1 		<= GCLK0;
GCLK0_val2      <= GCLK0_val1;

GCLK90_val1 		<= GCLK90;
GCLK90_val2     <= GCLK90_val1;

GCLK180_val1 		<= GCLK180;
GCLK180_val2    <= GCLK180_val1;

GCLK270_val1 		<= GCLK270;
GCLK270_val2    <= GCLK270_val1;

--*****************************************************************************************
-- Instantiate QDR-II Memory Interface clocking module
--*****************************************************************************************

QDR_interface_clocks : qdr2_clocks 
port map (  USER_CLK 			=> CLK200,
            USER_CLK_N  => CLK200N,
            RESET 			=> USER_RESET, 
            CLK_BUF 			=> CLK_BUF,
            GCLK0 			=> GCLK0,
            GCLK90 			=> GCLK90,
            GCLK180 			=> GCLK180,
            GCLK270 			=> GCLK270,
            CLKDIV2 			=> CLK_DIV2,
            LOCKED_DCM 	=> DCM_LOCKED );
		
--*****************************************************************************************
-- Instantiate QDR-II Memory Interface 
--*****************************************************************************************

QDR_Interface_B : qdr2_burst_4_body
port map ( USER_DWL 			   => Cout_WDataL, 
           USER_DWH 			   => Cout_WDataH,
           USER_Q 			   => DataR, 
           CLK_BUF 			   => CLK_BUF,
           CLK0E 			   => GCLK0_val2,--GCLK0,
           CLK90E 			   => GCLK90_val2,--GCLK90,
           CLK180E 			   => GCLK180_val2,
           CLK270E 			   => GCLK270_val2,
           LOCKED_DCM_PRI 	=> DCM_LOCKED,
           R_n_recapture   => R_n_recapture,
           USER_R_n 		     => R_n, 
           USER_W_n 			   => W_n,
           USER_BW_n 			   => "00",
           USER_RESET 		   => DCM_LOCKED_n,
           USER_DATA_VALID => UserDataValid,
           QDR_Q 			   => mem_Q,
           QDR_D 			   => mem_D,
           sys_rst180_val  => sys_rst180,
           QDR_CQ 			   => mem_CQ,
           QDR_CQ_n 			   => mem_CQ_n,
           TEST_RESET_0			 => Reset_CLK0
           );   
                                    
--*****************************************************************************************
-- Reset module, specific to ML365 
--*****************************************************************************************                                    
                                                        
ML365_RESET : QDR2_RESET port map ( ML365_RESET => Reset,
			            USER_RESET  => USER_RESET);
			    

 
end arc_QDR_LC_TOP;