📄 data_path.vhd
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v2p_qdr2_input_buffer0 : v2p_qdr2_input_buffer port map
( qdr2_in => qdr2_cq(0),
read_data_in => cq_int_delay_in0
);
--**************************************************************************************************
-- CQ Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
cq_delay0_col0 :cq_delay port map (
clk_in => cq_int_delay_in0,
sel_in => delay_sel,
clk_out => cq_delayed_col0(0)
);
cq_delay0_col1 :cq_delay port map (
clk_in => cq_int_delay_in0,
sel_in => delay_sel,
clk_out => cq_delayed_col1(0)
);
----***************************************************************************************************
---- CQ Divide by 2 instantiations
----***************************************************************************************************
FD_R_n_0 : FD port map (
Q => rst_cq_div_reg_fd1,
C => cq_delayed_col1(0),
D => rst_cq_div
);
qdr2_cq_div0 : qdr2_cq_div port map
(
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
rst_cq_div => rst_cq_div_reg_fd1,
cq_tranfert_col1 => cq_div_transfert_0_col0,
cq_tranfert_col0 => cq_div_transfert_0_col1
);
----****************************************************************************************************************
---- Transfer done instantiations (One instantiation per strobe)
----****************************************************************************************************************
qdr2_transfer_done0 : qdr2_transfer_done port map
( clk0 => clk,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
reset => reset_r,
reset90 => reset90_r,
reset180 => reset180_r,
reset270 => reset270_r,
cq_div => cq_div_transfert_0_col1,
transfer_done0 => transfer_done_00,
transfer_done1 => transfer_done_01,
transfer_done2 => transfer_done_02,
transfer_done3 => transfer_done_03
);
----****************************************************************************************************************
---- Generation of the synchronous CE for the data capture FD.
----****************************************************************************************************************
cq_delayed_col0_0_inv <= not (cq_delayed_col0(0));
FD_R_n_0_DC: FD port map
( Q => CE_R_FB0,
C => cq_delayed_col1(0), --changed col1 to col0
D => rst_cq_div
);
FD_R_n_1_DC: FD port map
( Q => CE_R_FB1,
C => cq_delayed_col0_0_inv,
D => CE_R_FB0
);
FD_R_n_2_DC: FD port map
( Q => CE_R_FB2,
C => cq_delayed_col1(0), --changed col1 to col0
D => CE_R_FB0
);
FD_R_n_3_DC : FD port map
( Q => CE_R_FB3,
C => cq_delayed_col0_0_inv,
D => CE_R_FB1);
----******************************************************************************************************************************
---- Q Data bits instantiations (36-bits)
----******************************************************************************************************************************
qdr2_qbit_0 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(0),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(0),
fbit_1 => fbit_1(0),
fbit_2 => fbit_2(0),
fbit_3 => fbit_3(0)
);
qdr2_qbit_1 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(1),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(1),
fbit_1 => fbit_1(1),
fbit_2 => fbit_2(1),
fbit_3 => fbit_3(1)
);
qdr2_qbit_2 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(2),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(2),
fbit_1 => fbit_1(2),
fbit_2 => fbit_2(2),
fbit_3 => fbit_3(2)
);
qdr2_qbit_3 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(3),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(3),
fbit_1 => fbit_1(3),
fbit_2 => fbit_2(3),
fbit_3 => fbit_3(3)
);
qdr2_qbit_4 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(4),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(4),
fbit_1 => fbit_1(4),
fbit_2 => fbit_2(4),
fbit_3 => fbit_3(4)
);
qdr2_qbit_5 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(5),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(5),
fbit_1 => fbit_1(5),
fbit_2 => fbit_2(5),
fbit_3 => fbit_3(5)
);
qdr2_qbit_6 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(6),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(6),
fbit_1 => fbit_1(6),
fbit_2 => fbit_2(6),
fbit_3 => fbit_3(6)
);
qdr2_qbit_7 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(7),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(7),
fbit_1 => fbit_1(7),
fbit_2 => fbit_2(7),
fbit_3 => fbit_3(7)
);
qdr2_qbit_8 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(8),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(8),
fbit_1 => fbit_1(8),
fbit_2 => fbit_2(8),
fbit_3 => fbit_3(8)
);
qdr2_qbit_9 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(9),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(9),
fbit_1 => fbit_1(9),
fbit_2 => fbit_2(9),
fbit_3 => fbit_3(9)
);
qdr2_qbit_10 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(10),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(10),
fbit_1 => fbit_1(10),
fbit_2 => fbit_2(10),
fbit_3 => fbit_3(10)
);
qdr2_qbit_11 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(11),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(11),
fbit_1 => fbit_1(11),
fbit_2 => fbit_2(11),
fbit_3 => fbit_3(11)
);
qdr2_qbit_12 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(12),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(12),
fbit_1 => fbit_1(12),
fbit_2 => fbit_2(12),
fbit_3 => fbit_3(12)
);
qdr2_qbit_13 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(13),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(13),
fbit_1 => fbit_1(13),
fbit_2 => fbit_2(13),
fbit_3 => fbit_3(13)
);
qdr2_qbit_14 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(14),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(14),
fbit_1 => fbit_1(14),
fbit_2 => fbit_2(14),
fbit_3 => fbit_3(14)
);
qdr2_qbit_15 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(15),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(15),
fbit_1 => fbit_1(15),
fbit_2 => fbit_2(15),
fbit_3 => fbit_3(15)
);
qdr2_qbit_16 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(16),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(16),
fbit_1 => fbit_1(16),
fbit_2 => fbit_2(16),
fbit_3 => fbit_3(16)
);
qdr2_qbit_17 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(17),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(17),
fbit_1 => fbit_1(17),
fbit_2 => fbit_2(17),
fbit_3 => fbit_3(17)
);
--****************************************************************************************************************************
RAM_18D_cq0_fbit0 : RAM_18D port map (
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_00,
D => fbit_0(17 downto 0),
DPO => fifo_00_data_out );
RAM_18D_cq0_fbit1 : RAM_18D port map (
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_01,
D => fbit_1(17 downto 0),
DPO => fifo_01_data_out );
RAM_18D_cq0_fbit2 : RAM_18D port map (
A0 => fifo_02_wr_addr(0),
A1 => fifo_02_wr_addr(1),
A2 => fifo_02_wr_addr(2),
A3 => fifo_02_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_02,
D => fbit_2(17 downto 0),
DPO => fifo_02_data_out );
RAM_18D_cq0_fbit3 : RAM_18D port map (
A0 => fifo_03_wr_addr(0),
A1 => fifo_03_wr_addr(1),
A2 => fifo_03_wr_addr(2),
A3 => fifo_03_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_03,
D => fbit_3(17 downto 0),
DPO => fifo_03_data_out );
end arc_data_path;
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