📄 qdr2_burst_4_body.vhd
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-- Generation of the reset signal in the different clock domains
process (CLK0E)
begin
if CLK0E'event and CLK0E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst0_o <= '1';
sys_rst0_1 <= '1';
sys_rst0 <= '1';
else
sys_rst0_o <= '0';
sys_rst0_1 <= sys_rst0_o;
sys_rst0 <= sys_rst0_1;
end if;
end if;
end process;
process (CLK90E)
begin
if CLK90E'event and CLK90E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst90_o <= '1';
sys_rst90_1 <= '1';
sys_rst90 <= '1';
else
sys_rst90_o <= '0';
sys_rst90_1 <= sys_rst90_o;
sys_rst90 <= sys_rst90_1;
end if;
end if;
end process;
process (CLK180E)
begin
if CLK180E'event and CLK180E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst180_o <= '1';
sys_rst180_1 <= '1';
sys_rst180 <= '1';
else
sys_rst180_o <= '0';
sys_rst180_1 <= sys_rst180_o;
sys_rst180 <= sys_rst180_1;
end if;
end if;
end process;
process (CLK270E)
begin
if CLK270E'event and CLK270E = '1' then
if RESET ='1' or LOCKED_DCM_PRI = '0' then
sys_rst270_o <= '1';
sys_rst270_1 <= '1';
sys_rst270 <= '1';
else
sys_rst270_o <= '0';
sys_rst270_1 <= sys_rst270_o;
sys_rst270 <= sys_rst270_1;
end if;
end if;
end process;
-- Input buffers declaration
INST_QDR_IBUF_R_n : IBUF_HSTL_II_18 port map (O => R_n_recapture , I => QDR_R_n_int );
-- OBUF instanciations
--INST_QDR_OBUF_BW : OBUF_HSTL_II_18 port map (O => QDR_BW_n(3 downto 0) , I => USER_BW_n(3 downto 0));
--INST_QDR_OBUF_BW(3 downto 0) : OBUF_HSTL_II_18 port map (O => QDR_BW_n, I => USER_BW_n);
g1 : for i1 in 0 to 7 generate
INST_QDR_OBUF_BW : OBUF_HSTL_II_18 port map (O => QDR_BW_n(i1), I => USER_BW_n(i1));
end generate;
-- Driving C signals at high
INST_QDR_OBUF_C0 : OBUF_HSTL_II_18 port map (O => QDR_C0 , I => HIGH);
INST_QDR_OBUF_C0_n : OBUF_HSTL_II_18 port map (O => QDR_C0_n , I => HIGH );
INST_QDR_OBUF_C1 : OBUF_HSTL_II_18 port map (O => QDR_C1 , I => HIGH);
INST_QDR_OBUF_C1_n : OBUF_HSTL_II_18 port map (O => QDR_C1_n , I => HIGH );
-- Write data bus to QDR II SRAM device
g3 : for i3 in 0 to data_bits-1 generate
INST_QDR_OBUF_DWRITE : OBUF_HSTL_II_18 port map (I => D_data(i3) , O => QDR_D(i3) );
end generate;
--QDR_SA_BUF
g4 : for i4 in 0 to 17 generate
INST_QDR_OBUF_DADDR : OBUF_HSTL_II_18 port map( I => ADR(i4) ,O => QDR_SA(i4) );
end generate;
INST_QDR_OBUF_K0 : OBUF_HSTL_II_18 port map ( I => O_DDR_K0_OBUF , O=>QDR_K0 );
INST_QDR_OBUF_K0_n : OBUF_HSTL_II_18 port map ( I => O_DDR_K0_n_OBUF , O=>QDR_K0_n);
INST_QDR_OBUF_K1 : OBUF_HSTL_II_18 port map ( I => O_DDR_K1_OBUF , O=>QDR_K1 );
INST_QDR_OBUF_K1_n : OBUF_HSTL_II_18 port map ( I => O_DDR_K1_n_OBUF , O=>QDR_K1_n);
-- Other control signals and clocks
INST_QDR_OBUF_W_n : OBUF_HSTL_II_18 port map( I => W_BAR , O => QDR_W_n);
-- RAKCHOPR - Changed to "FDS" from "FD" to add RESET term to flop
R_n_FD_pipe : FDS port map (Q => R_n_FD ,
D => USER_R_n ,
C => CLK270E ,
S => RESET);
-- RAKCHOPR --DDR register in the IO
WRT_FD_R_n : FDDRRSE port map (Q => R_BAR ,
C0 => CLK270E ,
C1 => CLK90E ,
CE => HIGH ,
D0 => R_n_FD,
D1 => '1',
R => GND ,
S => RESET );
INST_QDR_OBUF_R_n_tr1 : OBUF_HSTL_II_18 port map (I => R_BAR , O => QDR_R_n ) ;
INST_QDR_OBUF_R_n : OBUF_HSTL_II_18 port map (I => ReadInProgress , O => QDR_R_n_ext);
-- Clock forwarding to the memory device
FDDR_K0 : FDDRRSE port map ( Q => O_DDR_K0_OBUF ,
C0 => CLK0E ,
C1 => CLK180E ,
CE => HIGH ,
D0 => HIGH ,
D1 => GND ,
R => GND ,
S => GND ) ;
FDDR_K0_n : FDDRRSE port map (Q => O_DDR_K0_n_OBUF ,
C0 => CLK0E ,
C1=>CLK180E ,
CE=>HIGH ,
D0=>GND ,
D1=>HIGH ,
R=>GND ,
S=>GND );
-- Clock forwarding to the memory device
FDDR_K1 : FDDRRSE port map ( Q => O_DDR_K1_OBUF ,
C0 => CLK0E ,
C1 => CLK180E ,
CE => HIGH ,
D0 => HIGH ,
D1 => GND ,
R => GND ,
S => GND ) ;
FDDR_K1_n : FDDRRSE port map (Q => O_DDR_K1_n_OBUF ,
C0 => CLK0E ,
C1=>CLK180E ,
CE=>HIGH ,
D0=>GND ,
D1=>HIGH ,
R=>GND ,
S=>GND );
-- Write operation module
-- RAKCHOPR -- Added reset port
INST_Write : write_burst_4 port map (CLK90=>CLK90E ,
CLK270=>CLK270E ,
D0=>USER_DWH ,
D1=>USER_DWL ,
W_n=>USER_W_n ,
W_BAR=>W_BAR ,
Q=>D_data ,
CLK180=>CLK180E ,
RESET=>RESET );
--*****************************************************************************************
-- Calibration circuit
--*****************************************************************************************
FD_NoRead : FD port map (Q=>CalNoRead ,
D=>noReadCurrent ,
C=>CLK0E );
--CalNoRead out of CLK0 enables tap change from the calibration circuit when there is no read current
cal_inst : cal_top port map (clk => CLK_BUF ,
clk0 => CLK0E ,
clk0dcmlock => LOCKED_DCM_PRI ,
reset => sys_rst0 ,
okToSelTap => CalNoRead ,
tapForDqs => selTap );
-- Read datapath implementation
Read_data_path : data_path
port map( clk => CLK0E ,
clk90 => CLK90E ,
clk180 => CLK180E ,
clk270 => CLK270E ,
reset => sys_rst0 ,
reset90 => sys_rst90 ,
reset180 => sys_rst180 ,
reset270 => sys_rst270 ,
rst_cq_div => R_n_recapture ,
delay_sel => selTap ,
u_data_val => USER_DATA_VALID_val ,
qdr2_cq => CQ ,
qdr2_q => QDR_Q ,
user_output_data => USER_Q
);
-- Address bus: Read/Write multiplexer
process (CLK270E)
begin
if CLK270E'event and CLK270E = '1' then
if MUX_ADDR = '0' then -- !USER_W_n !USER_WRITE_E Write command active if USER_WRITE_E == 0
ADR <= USER_A_READ; -- AD_Write; USER_A_WRITE A_READ_FD
else
ADR <= A_WRITE_FD; -- AD_Read;A_READ_FD
end if;
end if;
end process;
-- Pipeline for Write address
g2 : for i2 in 0 to 17 generate
FD_AW1 : FD port map (Q => A_WRITE_FD(i2), D => USER_A_WRITE(i2), C => CLK270E );
end generate;
g5 : for i5 in 0 to 17 generate
FD_AR : FD port map (Q => A_READ_FD(i5), D => USER_A_READ(i5), C => CLK0E );
end generate;
-- Signal R_n_ext generation for synchronous scheme
QDR_R_n_ext_stage1_n <= not QDR_R_n_ext_stage1;
FD_R_n_1 : FDS port map (Q => QDR_R_n_ext_stage1 , C => CLK270E , D => USER_READ_E_val , S => RESET ); -- When reset, read command at 1
FD_R_n_2 : FDS port map (Q => QDR_R_n_ext_stage2 , C => CLK180E , D => QDR_R_n_ext_stage1_n , S => RESET ); -- When reset, read command at 1
FD_R_n_3 : FDS port map (Q => QDR_R_n_ext_stage3 , C => CLK90E , D => QDR_R_n_ext_stage2 , S => RESET ); -- When reset, read command at 1 modified to CLK90
-- State machine for controlling the QDR SRAM interface read and write accesses
ctrl_access : qdr2_fsm_access port map( CLK => CLK180E ,
RESET => sys_rst180 ,
USER_W_n => USER_W_n ,
USER_R_n => USER_R_n ,
WRITE_E => USER_WRITE_E ,
READ_E => USER_READ_E_val ,
CLK_A_RD => CLK0E ,
MUX_ADR_RD => MUX_ADDR) ;
end arc_qdr2_burst_4_body;
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