qdr_lc_top.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

--*****************************************************************************************
--** 
--**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
--** 
--**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         VHDL instanciation
--**
--*****************************************************************************************
--**
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--**              provided to you "as is". Xilinx and its licensors make and you 
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--**              particular purpose. Xilinx does not warrant that the functions 
--**              contained in these designs will meet your requirements, or that the
--**              operation of these designs will be uninterrupted or error free, or 
--**              that defects in the Designs will be corrected. Furthermore, Xilinx 
--**              does not warrant or make any representations regarding use or the 
--**              results of the use of the designs in terms of correctness, accuracy, 
--**              reliability, or otherwise. 
--**
--**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
--**              liable for any loss of data, lost profits, cost or procurement of 
--**              substitute goods or services, or for any special, incidental, 
--**              consequential, or indirect damages arising from the use or operation 
--**              of the designs or accompanying documentation, however caused and on 
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--**              any limited remedies herein. 
--**
--*****************************************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity QDR_LC_TOP is 
generic (
   -- Constant Parameters
	addr_bits 		: INTEGER := 18;
	data_bits 		: INTEGER := 72 );
	
port( CLK200     : in std_logic;
	CLK200N    : in std_logic; 
	Reset      : in std_logic; 
	Result_Reg : out std_logic; 
	mem_D      : out std_logic_vector(data_bits-1 downto 0); 
	mem_Q	     : in std_logic_vector(data_bits-1 downto 0); 
	mem_SA     : out std_logic_vector(addr_bits-1  downto 0); 
	mem_R_n    : out std_logic; 
	mem_W_n    : out std_logic; 
	mem_BW_n   : out std_logic_vector(7 downto 0); 
	mem_K0	     : out std_logic; 
	mem_K0_n    : out std_logic; 
	mem_K1	     : out std_logic; 
	mem_K1_n    : out std_logic; 
	mem_C0	     : out std_logic; 
	mem_C0_n    : out std_logic; 
	mem_C1	     : out std_logic; 
	mem_C1_n    : out std_logic; 
	mem_CQ0     : in std_logic; 
	mem_CQ0_n   : in std_logic; 
	mem_CQ1     : in std_logic; 
	mem_CQ1_n   : in std_logic; 
	mem_R_n_ext	 : out std_logic; 
	mem_R_n_int	 : in std_logic);
	
end QDR_LC_TOP;

architecture arc_QDR_LC_TOP of QDR_LC_TOP is 


component FD
  port( Q : out std_logic;
        D : in std_logic;
        C : in std_logic );
end component;

component  qdr2_burst_4_body 
port (  USER_DWL 			: in std_logic_vector(data_bits-1 downto 0);
        USER_DWH 			: in std_logic_vector(data_bits-1 downto 0);
        USER_Q			: out std_logic_vector(143 downto 0);
        USER_A_READ 			: in std_logic_vector(addr_bits-1 downto 0);
        USER_A_WRITE 			: in std_logic_vector(addr_bits-1 downto 0);
        CLK_BUF			: in std_logic;
        CLK0E			: in std_logic;
        CLK90E			: in std_logic;
        CLK180E			: in std_logic;
        CLK270E			: in std_logic;
        LOCKED_DCM_PRI		: in std_logic;
        USER_R_n			: in std_logic;
        USER_W_n			: in std_logic;
        USER_BW_n			: in std_logic_vector(7 downto 0);
        USER_RESET			: in std_logic;
        USER_DATA_VALID	: out std_logic;
        QDR_Q			: in std_logic_vector(data_bits-1 downto 0);
        QDR_D			: out std_logic_vector(data_bits-1 downto 0);
        QDR_SA			: out std_logic_vector(addr_bits-1  downto 0);
        QDR_R_n			: out std_logic;
        QDR_W_n			: out std_logic;
        QDR_BW_n			: out std_logic_vector(7 downto 0);
        QDR_K0			: out std_logic;
        QDR_K0_n			: out std_logic;
        QDR_K1			: out std_logic;
        QDR_K1_n			: out std_logic;
        QDR_C0			: out std_logic;
        QDR_C0_n			: out std_logic;
        QDR_C1			: out std_logic;
        QDR_C1_n			: out std_logic;
        QDR_CQ0			: in std_logic;
        QDR_CQ0_n			: in std_logic;
        QDR_CQ1			: in std_logic;
        QDR_CQ1_n			: in std_logic;
        QDR_R_n_ext			: out std_logic;
        QDR_R_n_int			: in std_logic;
        TEST_RESET_0			: out std_logic
        );
end component;

component QDR2_RESET
port( ML365_RESET : in std_logic ;
      USER_RESET  : out std_logic);
end component;

component qdr2_clocks
 port ( 	USER_CLK 		: in std_logic;
		USER_CLK_N 		: in std_logic;
		RESET 		: in std_logic;
        	CLK_BUF 		: out std_logic;
		GCLK0 		: out std_logic;
        	GCLK90 		: out std_logic;
		GCLK180 		: out std_logic;
        	GCLK270 		: out std_logic;
            CLKDIV2		: out std_logic;
            LOCKED_DCM 		: out std_logic );

end component;

component counter_4 
port (counter : out std_logic_vector(1 downto 0);
      inclock : in std_logic;
      reset	  : in std_logic);
end component;

component OBUF_HSTL_II_18 
port (O : out std_logic ; 
      I : in std_logic); 
end component;

component concat2to36Data 
port (Sortie  : out std_logic_vector(data_bits-1 downto 0);
	inclock : in std_logic;
	counter : in std_logic_vector(1 downto 0)	);
end component;
	
component counter_262144 
port(COut2	: out std_logic_vector(addr_bits-1  downto 0);
     inc    : in std_logic;
     reset	: in std_logic);     
end component;     

component OBUF_LVDCI_25 
port (O : out std_logic;
      I : in std_logic); 
end component;   

component delay
port(Si_In : in std_logic;
     Si_Out: out std_logic;
     Clock : in std_logic;
     Reset : in std_logic);
end component;

type s_m is (Start, GetReady, WriteCycle, ReadCycle);
signal CurrentState  : s_m;
signal  NextState 		 : s_m;
	
signal DataR 			: std_logic_vector(143 downto 0) ;
signal AddrW 			: std_logic_vector(addr_bits-1  downto 0) ;
signal AddrW_1int			: std_logic_vector(addr_bits-1  downto 0) ;
signal AddrW_2int			: std_logic_vector(addr_bits-1  downto 0) ;
signal AddrR			: std_logic_vector(addr_bits-1  downto 0) ; 
signal FD_UserDataValid 	: std_logic ;
signal FD_Data_R 			: std_logic_vector(143 downto 0) ;
signal mem_D_val 			: std_logic_vector(data_bits-1 downto 0) ; 
signal mem_Q_val 			: std_logic_vector(data_bits-1 downto 0) ; 
signal mem_SA_val 		: std_logic_vector(addr_bits-1  downto 0) ; 
signal UserDataValid 		: std_logic ;
signal Counter_outL 		: std_logic_vector(1 downto 0) ;
signal Counter_outH 		: std_logic_vector(1 downto 0) ;
signal ThisIsAGo 			: std_logic ;
signal Reset_CLK0 		: std_logic ;
signal Reset_CLK90 		: std_logic ;
signal To_concatenate 		: std_logic_vector(1 downto 0) ;
signal Reference_Data 		: std_logic_vector(data_bits-1 downto 0) ;
signal FD1_Reference_Data : std_logic_vector(data_bits-1 downto 0) ;
signal FD2_Reference_Data : std_logic_vector(data_bits-1 downto 0) ;
signal FD3_Reference_Data : std_logic_vector(data_bits-1 downto 0) ;
signal WCtrl_BUF 			  : std_logic ;
signal RCtrl_BUF 			  : std_logic ;
signal DCM_LCK_BUF 			  : std_logic ;
signal D0_capture_BUF 		  : std_logic ;
signal Reference_Data_BUF : std_logic ;

signal Cout_WDataL 			: std_logic_vector(data_bits-1 downto 0) ;
signal Cout_WDataH 			: std_logic_vector(data_bits-1 downto 0) ;

signal  ResetCount 			: std_logic ;
signal  R_n 			: std_logic ;
signal  W_n 			: std_logic ;
signal  Result 			: std_logic ;
signal  Result_BUF 			: std_logic ;
signal  Status_Ctrl_Operation : std_logic ;
signal  Status_Ctrl_Operation_buf : std_logic ;

--signal  CurrentState : std_logic_vector(1 downto 0) ;
--signal  NextState 		 : std_logic_vector(1 downto 0) ;

--*****************************************************************************************
-- Signal between qdr2_clocks qdr2_burst_4_body
--*****************************************************************************************

signal CLK_BUF 		: std_logic ;
signal GCLK0 		 : std_logic ;
signal GCLK90 		 : std_logic ;
signal GCLK180   : std_logic ;
signal GCLK270   : std_logic ;
signal CLK_DIV2  : std_logic ;
signal DCM_LOCKED: std_logic ;
     
signal USER_RESET 				: std_logic ;
signal  GCLK0_2 				: std_logic ;
signal DCM_LOCKED_n 				: std_logic;
signal GCLK0_2_n 				: std_logic;
signal FD_UserDataValid_n 				: std_logic;



 
begin 

DCM_LCK_BUF <= DCM_LOCKED;
DCM_LOCKED_n <= not DCM_LOCKED;
GCLK0_2_n <= (not GCLK0_2);
FD_UserDataValid_n <= not FD_UserDataValid;
mem_D     <= mem_D_val;
mem_Q_val <= mem_Q ;
mem_SA    <= mem_SA_val; 
--*****************************************************************************************
-- Pipeline stage for write address
--*****************************************************************************************

FD_UDV 	       : FD port map  ( Q => FD_UserDataValid , D => UserDataValid, C => GCLK90);  

g1: for i1 in 0 to 143 generate
FD_READ_DATA	  : FD port map  ( Q => FD_Data_R(i1), D =>  DataR(i1), C => GCLK90);
end generate;   

g2: for i2 in 0 to 71 generate
FD_REFDATA_ST1 : FD port map  ( Q => FD1_Reference_Data(i2), D => Reference_Data(i2), C => GCLK90); 
end generate;   

g3: for i3 in 0 to 71 generate