concat2to36data.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity concat2to36Data is
port ( Sortie  : out std_logic_vector(71 downto 0);
       inclock : in std_logic;
       counter : in std_logic_vector(1 downto 0));
end concat2to36Data;

architecture arc_concat2to36Data of concat2to36Data is 
begin
process(inclock)
begin
	if inclock'event and inclock ='1' then
	Sortie <= ( counter & counter & counter & counter & counter & counter & counter & counter & counter &
		    counter & counter & counter & counter & counter & counter & counter & counter & counter &
		    counter & counter & counter & counter & counter & counter & counter & counter & counter &
		    counter & counter & counter & counter & counter & counter & counter & counter & counter );
	end if;
end process;	

end arc_concat2to36Data;