📄 data_path.vhd
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fbit_1 => fbit_1(51),
fbit_2 => fbit_2(51),
fbit_3 => fbit_3(51)
);
qdr2_qbit_34 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(52),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(52),
fbit_1 => fbit_1(52),
fbit_2 => fbit_2(52),
fbit_3 => fbit_3(52)
);
qdr2_qbit_35 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(53),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(53),
fbit_1 => fbit_1(53),
fbit_2 => fbit_2(53),
fbit_3 => fbit_3(53)
);
qdr2_qbit_bar_18 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(54),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(54),
fbit_1 => fbit_1(54),
fbit_2 => fbit_2(54),
fbit_3 => fbit_3(54)
);
qdr2_qbit_bar_19 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(55),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(55),
fbit_1 => fbit_1(55),
fbit_2 => fbit_2(55),
fbit_3 => fbit_3(55)
);
qdr2_qbit_bar_20 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(56),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(56),
fbit_1 => fbit_1(56),
fbit_2 => fbit_2(56),
fbit_3 => fbit_3(56)
);
qdr2_qbit_bar_21 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(57),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(57),
fbit_1 => fbit_1(57),
fbit_2 => fbit_2(57),
fbit_3 => fbit_3(57)
);
qdr2_qbit_bar_22 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(58),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(58),
fbit_1 => fbit_1(58),
fbit_2 => fbit_2(58),
fbit_3 => fbit_3(58)
);
qdr2_qbit_bar_23 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(59),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(59),
fbit_1 => fbit_1(59),
fbit_2 => fbit_2(59),
fbit_3 => fbit_3(59)
);
qdr2_qbit_bar_24 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(60),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(60),
fbit_1 => fbit_1(60),
fbit_2 => fbit_2(60),
fbit_3 => fbit_3(60)
);
qdr2_qbit_bar_25 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(61),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(61),
fbit_1 => fbit_1(61),
fbit_2 => fbit_2(61),
fbit_3 => fbit_3(61)
);
qdr2_qbit_bar_26 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(62),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(62),
fbit_1 => fbit_1(62),
fbit_2 => fbit_2(62),
fbit_3 => fbit_3(62)
);
qdr2_qbit_bar_27 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(63),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(63),
fbit_1 => fbit_1(63),
fbit_2 => fbit_2(63),
fbit_3 => fbit_3(63)
);
qdr2_qbit_bar_28 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(64),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(64),
fbit_1 => fbit_1(64),
fbit_2 => fbit_2(64),
fbit_3 => fbit_3(64)
);
qdr2_qbit_bar_29 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(65),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(65),
fbit_1 => fbit_1(65),
fbit_2 => fbit_2(65),
fbit_3 => fbit_3(65)
);
qdr2_qbit_bar_30 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(66),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(66),
fbit_1 => fbit_1(66),
fbit_2 => fbit_2(66),
fbit_3 => fbit_3(66)
);
qdr2_qbit_bar_31 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(67),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(67),
fbit_1 => fbit_1(67),
fbit_2 => fbit_2(67),
fbit_3 => fbit_3(67)
);
qdr2_qbit_bar_32 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(68),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(68),
fbit_1 => fbit_1(68),
fbit_2 => fbit_2(68),
fbit_3 => fbit_3(68)
);
qdr2_qbit_bar_33 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(69),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(69),
fbit_1 => fbit_1(69),
fbit_2 => fbit_2(69),
fbit_3 => fbit_3(69)
);
qdr2_qbit_bar_34 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(70),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(70),
fbit_1 => fbit_1(70),
fbit_2 => fbit_2(70),
fbit_3 => fbit_3(70)
);
qdr2_qbit_bar_35 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
qdr2_q => qdr2_q(71),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(71),
fbit_1 => fbit_1(71),
fbit_2 => fbit_2(71),
fbit_3 => fbit_3(71)
);
--****************************************************************************************************************************
RAM_18D_cq0_fbit0 : RAM_18D port map (
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_00,
D => fbit_0(17 downto 0),
DPO => fifo_00_data_out );
RAM_18D_cq0_fbit1 : RAM_18D port map (
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_01,
D => fbit_1(17 downto 0),
DPO => fifo_01_data_out );
RAM_18D_cq0_fbit2 : RAM_18D port map (
A0 => fifo_02_wr_addr(0),
A1 => fifo_02_wr_addr(1),
A2 => fifo_02_wr_addr(2),
A3 => fifo_02_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_02,
D => fbit_2(17 downto 0),
DPO => fifo_02_data_out );
RAM_18D_cq0_fbit3 : RAM_18D port map (
A0 => fifo_03_wr_addr(0),
A1 => fifo_03_wr_addr(1),
A2 => fifo_03_wr_addr(2),
A3 => fifo_03_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_03,
D => fbit_3(17 downto 0),
DPO => fifo_03_data_out );
RAM_18D_cq1_fbit0 : RAM_18D port map (
A0 => fifo_10_wr_addr(0),
A1 => fifo_10_wr_addr(1),
A2 => fifo_10_wr_addr(2),
A3 => fifo_10_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_10,
D => fbit_0(35 downto 18),
DPO => fifo_10_data_out );
RAM_18D_cq1_fbit1 : RAM_18D port map (
A0 => fifo_11_wr_addr(0),
A1 => fifo_11_wr_addr(1),
A2 => fifo_11_wr_addr(2),
A3 => fifo_11_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_11,
D => fbit_1(35 downto 18),
DPO => fifo_11_data_out );
RAM_18D_cq1_fbit2 : RAM_18D port map (
A0 => fifo_12_wr_addr(0),
A1 => fifo_12_wr_addr(1),
A2 => fifo_12_wr_addr(2),
A3 => fifo_12_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_12,
D => fbit_2(35 downto 18),
DPO => fifo_12_data_out );
RAM_18D_cq1_fbit3 : RAM_18D port map (
A0 => fifo_13_wr_addr(0),
A1 => fifo_13_wr_addr(1),
A2 => fifo_13_wr_addr(2),
A3 => fi⌨️ 快捷键说明
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