📄 data_path.vhd
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CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(24),
fbit_1 => fbit_1(24),
fbit_2 => fbit_2(24),
fbit_3 => fbit_3(24)
);
qdr2_qbit_bar_7 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(25),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(25),
fbit_1 => fbit_1(25),
fbit_2 => fbit_2(25),
fbit_3 => fbit_3(25)
);
qdr2_qbit_bar_8 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(26),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(26),
fbit_1 => fbit_1(26),
fbit_2 => fbit_2(26),
fbit_3 => fbit_3(26)
);
qdr2_qbit_bar_9 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(27),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(27),
fbit_1 => fbit_1(27),
fbit_2 => fbit_2(27),
fbit_3 => fbit_3(27)
);
qdr2_qbit_bar_10 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(28),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(28),
fbit_1 => fbit_1(28),
fbit_2 => fbit_2(28),
fbit_3 => fbit_3(28)
);
qdr2_qbit_bar_11 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(29),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(29),
fbit_1 => fbit_1(29),
fbit_2 => fbit_2(29),
fbit_3 => fbit_3(29)
);
qdr2_qbit_bar_12 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(30),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(30),
fbit_1 => fbit_1(30),
fbit_2 => fbit_2(30),
fbit_3 => fbit_3(30)
);
qdr2_qbit_bar_13 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(31),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(31),
fbit_1 => fbit_1(31),
fbit_2 => fbit_2(31),
fbit_3 => fbit_3(31)
);
qdr2_qbit_bar_14 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(32),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(32),
fbit_1 => fbit_1(32),
fbit_2 => fbit_2(32),
fbit_3 => fbit_3(32)
);
qdr2_qbit_bar_15 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(33),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(33),
fbit_1 => fbit_1(33),
fbit_2 => fbit_2(33),
fbit_3 => fbit_3(33)
);
qdr2_qbit_bar_16 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(34),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(34),
fbit_1 => fbit_1(34),
fbit_2 => fbit_2(34),
fbit_3 => fbit_3(34)
);
qdr2_qbit_bar_17 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(35),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(35),
fbit_1 => fbit_1(35),
fbit_2 => fbit_2(35),
fbit_3 => fbit_3(35)
);
qdr2_qbit_18 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(36),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(36),
fbit_1 => fbit_1(36),
fbit_2 => fbit_2(36),
fbit_3 => fbit_3(36)
);
qdr2_qbit_19 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(37),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(37),
fbit_1 => fbit_1(37),
fbit_2 => fbit_2(37),
fbit_3 => fbit_3(37)
);
qdr2_qbit_20 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(38),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(38),
fbit_1 => fbit_1(38),
fbit_2 => fbit_2(38),
fbit_3 => fbit_3(38)
);
qdr2_qbit_21 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(39),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(39),
fbit_1 => fbit_1(39),
fbit_2 => fbit_2(39),
fbit_3 => fbit_3(39)
);
qdr2_qbit_22 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(40),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(40),
fbit_1 => fbit_1(40),
fbit_2 => fbit_2(40),
fbit_3 => fbit_3(40)
);
qdr2_qbit_23 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(41),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(41),
fbit_1 => fbit_1(41),
fbit_2 => fbit_2(41),
fbit_3 => fbit_3(41)
);
qdr2_qbit_24 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(42),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(42),
fbit_1 => fbit_1(42),
fbit_2 => fbit_2(42),
fbit_3 => fbit_3(42)
);
qdr2_qbit_25 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(43),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(43),
fbit_1 => fbit_1(43),
fbit_2 => fbit_2(43),
fbit_3 => fbit_3(43)
);
qdr2_qbit_26 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(44),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(44),
fbit_1 => fbit_1(44),
fbit_2 => fbit_2(44),
fbit_3 => fbit_3(44)
);
qdr2_qbit_27 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(45),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(45),
fbit_1 => fbit_1(45),
fbit_2 => fbit_2(45),
fbit_3 => fbit_3(45)
);
qdr2_qbit_28 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(46),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(46),
fbit_1 => fbit_1(46),
fbit_2 => fbit_2(46),
fbit_3 => fbit_3(46)
);
qdr2_qbit_29 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(47),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(47),
fbit_1 => fbit_1(47),
fbit_2 => fbit_2(47),
fbit_3 => fbit_3(47)
);
qdr2_qbit_30 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(48),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(48),
fbit_1 => fbit_1(48),
fbit_2 => fbit_2(48),
fbit_3 => fbit_3(48)
);
qdr2_qbit_31 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(49),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(49),
fbit_1 => fbit_1(49),
fbit_2 => fbit_2(49),
fbit_3 => fbit_3(49)
);
qdr2_qbit_32 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(50),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(50),
fbit_1 => fbit_1(50),
fbit_2 => fbit_2(50),
fbit_3 => fbit_3(50)
);
qdr2_qbit_33 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
qdr2_q => qdr2_q(51),
CE_R_FB0 => CE_R_FB10,
CE_R_FB1 => CE_R_FB11,
CE_R_FB2 => CE_R_FB12,
CE_R_FB3 => CE_R_FB13,
fbit_0 => fbit_0(51),
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