📄 data_path.vhd
字号:
);
FD_R_n_02_DC: FD port map
( Q => CE_R_FB02,
C => cq_delayed_col1(0), --changed col1 to col0
D => CE_R_FB00
);
FD_R_n_03_DC : FD port map
( Q => CE_R_FB03,
C => cq_delayed_col0_0_inv,
D => CE_R_FB01);
FD_R_n_10_DC: FD port map
( Q => CE_R_FB10,
C => cq_delayed_col1(2), --changed col1 to col0
D => rst_cq_div
);
FD_R_n_11_DC: FD port map
( Q => CE_R_FB11,
C => cq_delayed_col0_2_inv,
D => CE_R_FB10
);
FD_R_n_12_DC: FD port map
( Q => CE_R_FB12,
C => cq_delayed_col1(2), --changed col1 to col0
D => CE_R_FB10
);
FD_R_n_13_DC : FD port map
( Q => CE_R_FB13,
C => cq_delayed_col0_2_inv,
D => CE_R_FB11);
----******************************************************************************************************************************
---- Q Data bits instantiations (36-bits)
----******************************************************************************************************************************
qdr2_qbit_0 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(0),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(0),
fbit_1 => fbit_1(0),
fbit_2 => fbit_2(0),
fbit_3 => fbit_3(0)
);
qdr2_qbit_1 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(1),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(1),
fbit_1 => fbit_1(1),
fbit_2 => fbit_2(1),
fbit_3 => fbit_3(1)
);
qdr2_qbit_2 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(2),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(2),
fbit_1 => fbit_1(2),
fbit_2 => fbit_2(2),
fbit_3 => fbit_3(2)
);
qdr2_qbit_3 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(3),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(3),
fbit_1 => fbit_1(3),
fbit_2 => fbit_2(3),
fbit_3 => fbit_3(3)
);
qdr2_qbit_4 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(4),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(4),
fbit_1 => fbit_1(4),
fbit_2 => fbit_2(4),
fbit_3 => fbit_3(4)
);
qdr2_qbit_5 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(5),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(5),
fbit_1 => fbit_1(5),
fbit_2 => fbit_2(5),
fbit_3 => fbit_3(5)
);
qdr2_qbit_6 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(6),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(6),
fbit_1 => fbit_1(6),
fbit_2 => fbit_2(6),
fbit_3 => fbit_3(6)
);
qdr2_qbit_7 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(7),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(7),
fbit_1 => fbit_1(7),
fbit_2 => fbit_2(7),
fbit_3 => fbit_3(7)
);
qdr2_qbit_8 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(8),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(8),
fbit_1 => fbit_1(8),
fbit_2 => fbit_2(8),
fbit_3 => fbit_3(8)
);
qdr2_qbit_9 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(9),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(9),
fbit_1 => fbit_1(9),
fbit_2 => fbit_2(9),
fbit_3 => fbit_3(9)
);
qdr2_qbit_10 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(10),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(10),
fbit_1 => fbit_1(10),
fbit_2 => fbit_2(10),
fbit_3 => fbit_3(10)
);
qdr2_qbit_11 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(11),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(11),
fbit_1 => fbit_1(11),
fbit_2 => fbit_2(11),
fbit_3 => fbit_3(11)
);
qdr2_qbit_12 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(12),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(12),
fbit_1 => fbit_1(12),
fbit_2 => fbit_2(12),
fbit_3 => fbit_3(12)
);
qdr2_qbit_13 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(13),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(13),
fbit_1 => fbit_1(13),
fbit_2 => fbit_2(13),
fbit_3 => fbit_3(13)
);
qdr2_qbit_14 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(14),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(14),
fbit_1 => fbit_1(14),
fbit_2 => fbit_2(14),
fbit_3 => fbit_3(14)
);
qdr2_qbit_15 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(15),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(15),
fbit_1 => fbit_1(15),
fbit_2 => fbit_2(15),
fbit_3 => fbit_3(15)
);
qdr2_qbit_16 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(16),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(16),
fbit_1 => fbit_1(16),
fbit_2 => fbit_2(16),
fbit_3 => fbit_3(16)
);
qdr2_qbit_17 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(17),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(17),
fbit_1 => fbit_1(17),
fbit_2 => fbit_2(17),
fbit_3 => fbit_3(17)
);
qdr2_qbit_bar_0 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(18),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(18),
fbit_1 => fbit_1(18),
fbit_2 => fbit_2(18),
fbit_3 => fbit_3(18)
);
qdr2_qbit_bar_1 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(19),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(19),
fbit_1 => fbit_1(19),
fbit_2 => fbit_2(19),
fbit_3 => fbit_3(19)
);
qdr2_qbit_bar_2 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(20),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(20),
fbit_1 => fbit_1(20),
fbit_2 => fbit_2(20),
fbit_3 => fbit_3(20)
);
qdr2_qbit_bar_3 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(21),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(21),
fbit_1 => fbit_1(21),
fbit_2 => fbit_2(21),
fbit_3 => fbit_3(21)
);
qdr2_qbit_bar_4 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(22),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(22),
fbit_1 => fbit_1(22),
fbit_2 => fbit_2(22),
fbit_3 => fbit_3(22)
);
qdr2_qbit_bar_5 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(23),
CE_R_FB0 => CE_R_FB00,
CE_R_FB1 => CE_R_FB01,
CE_R_FB2 => CE_R_FB02,
CE_R_FB3 => CE_R_FB03,
fbit_0 => fbit_0(23),
fbit_1 => fbit_1(23),
fbit_2 => fbit_2(23),
fbit_3 => fbit_3(23)
);
qdr2_qbit_bar_6 : qdr2_qbit_cq_bar port map
( reset => reset270_r,
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
qdr2_q => qdr2_q(24),
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -