📄 data_path.vhd
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end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_12_wr_addr <= "0000";
elsif transfer_done_12 = '1' then
fifo_12_wr_addr <= fifo_12_wr_addr +"0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_13_wr_addr <= "0000";
elsif transfer_done_13 = '1' then
fifo_13_wr_addr <= fifo_13_wr_addr + "0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_20_wr_addr <= "0000";
elsif transfer_done_20 = '1' then
fifo_20_wr_addr <= fifo_20_wr_addr + "0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_21_wr_addr <= "0000";
elsif transfer_done_21 = '1' then
fifo_21_wr_addr <= fifo_21_wr_addr + "0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_22_wr_addr <= "0000";
elsif transfer_done_22 = '1' then
fifo_22_wr_addr <= fifo_22_wr_addr +"0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_23_wr_addr <= "0000";
elsif transfer_done_23 = '1' then
fifo_23_wr_addr <= fifo_23_wr_addr + "0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_30_wr_addr <= "0000";
elsif transfer_done_30 = '1' then
fifo_30_wr_addr <= fifo_30_wr_addr + "0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_31_wr_addr <= "0000";
elsif transfer_done_31 = '1' then
fifo_31_wr_addr <= fifo_31_wr_addr + "0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_32_wr_addr <= "0000";
elsif transfer_done_32 = '1' then
fifo_32_wr_addr <= fifo_32_wr_addr +"0001";
end if;
end if;
end process;
process (clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r ='1' then
fifo_33_wr_addr <= "0000";
elsif transfer_done_33 = '1' then
fifo_33_wr_addr <= fifo_33_wr_addr + "0001";
end if;
end if;
end process;
--*******************************************************************************************
user_output_reg : PROCESS
BEGIN
WAIT UNTIL clk90'event and clk90 = '1';
IF (reset90_r = '1') THEN
next_state <= '0';
fifo_00_rd_addr <= "0000";
fifo_02_rd_addr <= "0000";
user_output_data <= (others => '0');
ELSE
CASE next_state is
WHEN '0' =>
IF (read_valid_data_1 = '1') THEN
next_state <= '1';
fifo_00_rd_addr <= fifo_00_rd_addr + "0001";
user_output_data <= (fifo_30_data_out & fifo_20_data_out & fifo_10_data_out & fifo_00_data_out & fifo_31_data_out & fifo_21_data_out & fifo_11_data_out & fifo_01_data_out);
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (read_valid_data_2 = '1') THEN
next_state <= '0';
fifo_02_rd_addr <= fifo_02_rd_addr + "0001";
user_output_data <= (fifo_32_data_out & fifo_22_data_out &fifo_12_data_out & fifo_02_data_out & fifo_33_data_out & fifo_23_data_out & fifo_13_data_out & fifo_03_data_out);
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
fifo_00_rd_addr <= "0000";
fifo_02_rd_addr <= "0000";
user_output_data <= (others => '0');
END CASE;
END IF;
END PROCESS; -- user_output_reg
rd_data_valid_reg : PROCESS
BEGIN
WAIT UNTIL clk90'event and clk90 = '1';
IF (reset90_r = '1') THEN
fifo_11_not_empty_r <= '0';
fifo_13_not_empty_r <= '0';
rd_data_valid <= '0';
ELSE
fifo_11_not_empty_r <= fifo_11_not_empty;
fifo_13_not_empty_r <= fifo_13_not_empty;
rd_data_valid <= read_valid_data;
END IF;
END PROCESS; -- rd_data_valid_reg
--**********************************************************************
-- Reset flip-flops
--*********************************************************************/
rst0_r : FD port map (
Q => reset_r,
D => reset,
C => clk );
rst90_r : FD port map (
Q => reset90_r,
D => reset90,
C => clk90 );
rst180_r : FD port map (
Q => reset180_r,
D => reset180,
C => clk180 );
rst270_r : FD port map (
Q => reset270_r,
D => reset270,
C => clk270 );
--***********************************************************************
-- Read Data Capture Module Instantiations
--***********************************************************************
-- CQ IOB instantiations
--***********************************************************************
v2p_qdr2_input_buffer0 : v2p_qdr2_input_buffer port map
( qdr2_in => qdr2_cq(0),
read_data_in => cq_int_delay_in0
);
v2p_qdr2_input_buffer1 : v2p_qdr2_input_buffer port map
( qdr2_in => qdr2_cq(1),
read_data_in => cq_int_delay_in1
);
v2p_qdr2_input_buffer2 : v2p_qdr2_input_buffer port map
( qdr2_in => qdr2_cq(2),
read_data_in => cq_int_delay_in2
);
v2p_qdr2_input_buffer3 : v2p_qdr2_input_buffer port map
( qdr2_in => qdr2_cq(3),
read_data_in => cq_int_delay_in3
);
--**************************************************************************************************
-- CQ Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
cq_delay0_col0 :cq_delay port map (
clk_in => cq_int_delay_in0,
sel_in => delay_sel,
clk_out => cq_delayed_col0(0)
);
cq_delay0_col1 :cq_delay port map (
clk_in => cq_int_delay_in0,
sel_in => delay_sel,
clk_out => cq_delayed_col1(0)
);
cq_delay1_col0 :cq_delay port map (
clk_in => cq_int_delay_in1,
sel_in => delay_sel,
clk_out => cq_delayed_col0(1)
);
cq_delay1_col1 :cq_delay port map (
clk_in => cq_int_delay_in1,
sel_in => delay_sel,
clk_out => cq_delayed_col1(1)
);
cq_delay2_col0 :cq_delay port map (
clk_in => cq_int_delay_in2,
sel_in => delay_sel,
clk_out => cq_delayed_col0(2)
);
cq_delay2_col1 :cq_delay port map (
clk_in => cq_int_delay_in2,
sel_in => delay_sel,
clk_out => cq_delayed_col1(2)
);
cq_delay3_col0 :cq_delay port map (
clk_in => cq_int_delay_in3,
sel_in => delay_sel,
clk_out => cq_delayed_col0(3)
);
cq_delay3_col1 :cq_delay port map (
clk_in => cq_int_delay_in3,
sel_in => delay_sel,
clk_out => cq_delayed_col1(3)
);
----***************************************************************************************************
---- CQ Divide by 2 instantiations
----***************************************************************************************************
FD_R_n_0 : FD port map (
Q => rst_cq_div_reg_fd1,
C => cq_delayed_col1(0),
D => rst_cq_div
);
qdr2_cq_div0 : qdr2_cq_div port map
(
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
rst_cq_div => rst_cq_div_reg_fd1,
cq_tranfert_col1 => cq_div_transfert_0_col0,
cq_tranfert_col0 => cq_div_transfert_0_col1
);
qdr2_cq_bar_div0 : qdr2_cq_bar_div port map
(
cq => cq_delayed_col0(1),
cq1 => cq_delayed_col1(1),
rst_cq_div => rst_cq_div_reg_fd1,
cq_tranfert_col1 => cq_div_transfert_1_col0,
cq_tranfert_col0 => cq_div_transfert_1_col1
);
qdr2_cq_div1 : qdr2_cq_div port map
(
cq => cq_delayed_col0(2),
cq1 => cq_delayed_col1(2),
rst_cq_div => rst_cq_div_reg_fd1,
cq_tranfert_col1 => cq_div_transfert_2_col0,
cq_tranfert_col0 => cq_div_transfert_2_col1
);
qdr2_cq_bar_div1 : qdr2_cq_bar_div port map
(
cq => cq_delayed_col0(3),
cq1 => cq_delayed_col1(3),
rst_cq_div => rst_cq_div_reg_fd1,
cq_tranfert_col1 => cq_div_transfert_3_col0,
cq_tranfert_col0 => cq_div_transfert_3_col1
);
----****************************************************************************************************************
---- Transfer done instantiations (One instantiation per strobe)
----****************************************************************************************************************
qdr2_transfer_done0 : qdr2_transfer_done port map
( clk0 => clk,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
reset => reset_r,
reset90 => reset90_r,
reset180 => reset180_r,
reset270 => reset270_r,
cq_div => cq_div_transfert_0_col1,
transfer_done0 => transfer_done_00,
transfer_done1 => transfer_done_01,
transfer_done2 => transfer_done_02,
transfer_done3 => transfer_done_03
);
qdr2_transfer_done1 : qdr2_transfer_done port map
( clk0 =>clk,
clk90 =>clk90,
clk180 =>clk180,
clk270 =>clk270,
reset =>reset_r,
reset90 =>reset90_r,
reset180 =>reset180_r,
reset270 =>reset270_r,
cq_div =>cq_div_transfert_1_col1,
transfer_done0 =>transfer_done_10,
transfer_done1 =>transfer_done_11,
transfer_done2 =>transfer_done_12,
transfer_done3 =>transfer_done_13
);
qdr2_transfer_done2 : qdr2_transfer_done port map
( clk0 => clk,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
reset => reset_r,
reset90 => reset90_r,
reset180 => reset180_r,
reset270 => reset270_r,
cq_div => cq_div_transfert_2_col1,
transfer_done0 => transfer_done_20,
transfer_done1 => transfer_done_21,
transfer_done2 => transfer_done_22,
transfer_done3 => transfer_done_23
);
qdr2_transfer_done3 : qdr2_transfer_done port map
( clk0 =>clk,
clk90 =>clk90,
clk180 =>clk180,
clk270 =>clk270,
reset =>reset_r,
reset90 =>reset90_r,
reset180 =>reset180_r,
reset270 =>reset270_r,
cq_div =>cq_div_transfert_3_col1,
transfer_done0 =>transfer_done_30,
transfer_done1 =>transfer_done_31,
transfer_done2 =>transfer_done_32,
transfer_done3 =>transfer_done_33
);
----****************************************************************************************************************
---- Generation of the synchronous CE for the data capture FD.
----****************************************************************************************************************
cq_delayed_col0_0_inv <= not (cq_delayed_col0(0));
cq_delayed_col0_2_inv <= not (cq_delayed_col0(2));
FD_R_n_00_DC: FD port map
( Q => CE_R_FB00,
C => cq_delayed_col1(0), --changed col1 to col0
D => rst_cq_div
);
FD_R_n_01_DC: FD port map
( Q => CE_R_FB01,
C => cq_delayed_col0_0_inv,
D => CE_R_FB00
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