ram_18d.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 194 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity RAM_18D is
port(
       DPO: out  std_logic_vector (8 downto 0);  
       A0: in std_logic;   
       A1: in std_logic;   
       A2: in std_logic;   
       A3: in std_logic;   
       D: in std_logic_vector (8 downto 0);      
       DPRA0: in std_logic;
       DPRA1: in std_logic;
       DPRA2: in std_logic;
       DPRA3: in std_logic;
       WCLK: in std_logic;
       WE  : in std_logic   
     );
end RAM_18D;

architecture arc_RAM_18D of RAM_18D is
component RAM16X1D
  port (D     : in std_logic;
        WE    : in std_logic;
        WCLK  : in std_logic;
        A0    : in std_logic;
        A1    : in std_logic;
        A2    : in std_logic;
        A3    : in std_logic;
        DPRA0 : in std_logic;
        DPRA1 : in std_logic;
        DPRA2 : in std_logic;
        DPRA3 : in std_logic; 
        SPO   : out std_logic;
        DPO   : out std_logic);
end component;


begin
--parameter memory_width = 18 -1; // Size of the data bus -1

RAM16X1D_0 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(0), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(0)
			 );                                                                                                                                                                                                                                       
RAM16X1D_1 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(1), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(1)
			 );                                                                                                                                                                                                                                       
RAM16X1D_2 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(2), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(2)
			 );                                                                                                                                                                                                                                       
RAM16X1D_3 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(3), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(3)
			 );                                                                                                                                                                                                                                       
RAM16X1D_4 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(4), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(4)
			 );                                                                                                                                                                                                                                       
RAM16X1D_5 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(5), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(5)
			 );                                                                                                                                                                                                                                       
RAM16X1D_6 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(6), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(6)
			 );                                                                                                                                                                                                                                       
RAM16X1D_7 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(7), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(7)
			 );                                                                                                                                                                                                                                       
RAM16X1D_8 : RAM16X1D port map 			 
			   ( 
			   	 D 	=> D(8), 
				 WE	=> WE, 
				 WCLK	=> WCLK, 
				 A0	=> A0, 
				 A1	=> A1, 
				 A2	=> A2, 
				 A3	=> A3, 
				 DPRA0	=> DPRA0, 
				 DPRA1	=> DPRA1, 
				 DPRA2	=> DPRA2, 
				 DPRA3	=> DPRA3, 
				 SPO	=> open, 
				 DPO	=> DPO(8)
			 );                                                                                                                                                                                                                                       
end arc_RAM_18D;