📄 data_path.vhd
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ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (read_valid_data_2 = '1') THEN
next_state <= '0';
fifo_02_rd_addr <= fifo_02_rd_addr + "0001";
user_output_data <= (fifo_02_data_out & fifo_03_data_out);
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
fifo_00_rd_addr <= "0000";
fifo_02_rd_addr <= "0000";
user_output_data <= (others => '0');
END CASE;
END IF;
END PROCESS; -- user_output_reg
rd_data_valid_reg : PROCESS
BEGIN
WAIT UNTIL clk90'event and clk90 = '1';
IF (reset90_r = '1') THEN
fifo_11_not_empty_r <= '0';
fifo_13_not_empty_r <= '0';
rd_data_valid <= '0';
ELSE
fifo_11_not_empty_r <= fifo_11_not_empty;
fifo_13_not_empty_r <= fifo_13_not_empty;
rd_data_valid <= read_valid_data;
END IF;
END PROCESS; -- rd_data_valid_reg
--**********************************************************************
-- Reset flip-flops
--*********************************************************************/
rst0_r : FD port map (
Q => reset_r,
D => reset,
C => clk );
rst90_r : FD port map (
Q => reset90_r,
D => reset90,
C => clk90 );
rst180_r : FD port map (
Q => reset180_r,
D => reset180,
C => clk180 );
rst270_r : FD port map (
Q => reset270_r,
D => reset270,
C => clk270 );
--***********************************************************************
-- Read Data Capture Module Instantiations
--***********************************************************************
-- CQ IOB instantiations
--***********************************************************************
v2p_qdr2_input_buffer0 : v2p_qdr2_input_buffer port map
( qdr2_in => qdr2_cq(0),
read_data_in => cq_int_delay_in0
);
--**************************************************************************************************
-- CQ Internal Delay Circuit implemented in LUTs
--**************************************************************************************************
cq_delay0_col0 :cq_delay port map (
clk_in => cq_int_delay_in0,
sel_in => delay_sel,
clk_out => cq_delayed_col0(0)
);
cq_delay0_col1 :cq_delay port map (
clk_in => cq_int_delay_in0,
sel_in => delay_sel,
clk_out => cq_delayed_col1(0)
);
----***************************************************************************************************
---- CQ Divide by 2 instantiations
----***************************************************************************************************
FD_R_n_0 : FD port map (
Q => rst_cq_div_reg_fd1,
C => cq_delayed_col1(0),
D => rst_cq_div
);
qdr2_cq_div0 : qdr2_cq_div port map
(
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
rst_cq_div => rst_cq_div_reg_fd1,
cq_tranfert_col1 => cq_div_transfert_0_col0,
cq_tranfert_col0 => cq_div_transfert_0_col1
);
----****************************************************************************************************************
---- Transfer done instantiations (One instantiation per strobe)
----****************************************************************************************************************
qdr2_transfer_done0 : qdr2_transfer_done port map
( clk0 => clk,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
reset => reset_r,
reset90 => reset90_r,
reset180 => reset180_r,
reset270 => reset270_r,
cq_div => cq_div_transfert_0_col1,
transfer_done0 => transfer_done_00,
transfer_done1 => transfer_done_01,
transfer_done2 => transfer_done_02,
transfer_done3 => transfer_done_03
);
----****************************************************************************************************************
---- Generation of the synchronous CE for the data capture FD.
----****************************************************************************************************************
cq_delayed_col0_0_inv <= not (cq_delayed_col0(0));
FD_R_n_0_DC: FD port map
( Q => CE_R_FB0,
C => cq_delayed_col1(0), --changed col1 to col0
D => rst_cq_div
);
FD_R_n_1_DC: FD port map
( Q => CE_R_FB1,
C => cq_delayed_col0_0_inv,
D => CE_R_FB0
);
FD_R_n_2_DC: FD port map
( Q => CE_R_FB2,
C => cq_delayed_col1(0), --changed col1 to col0
D => CE_R_FB0
);
FD_R_n_3_DC : FD port map
( Q => CE_R_FB3,
C => cq_delayed_col0_0_inv,
D => CE_R_FB1);
----******************************************************************************************************************************
---- Q Data bits instantiations (36-bits)
----******************************************************************************************************************************
qdr2_qbit_0 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(0),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(0),
fbit_1 => fbit_1(0),
fbit_2 => fbit_2(0),
fbit_3 => fbit_3(0)
);
qdr2_qbit_1 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(1),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(1),
fbit_1 => fbit_1(1),
fbit_2 => fbit_2(1),
fbit_3 => fbit_3(1)
);
qdr2_qbit_2 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(2),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(2),
fbit_1 => fbit_1(2),
fbit_2 => fbit_2(2),
fbit_3 => fbit_3(2)
);
qdr2_qbit_3 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(3),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(3),
fbit_1 => fbit_1(3),
fbit_2 => fbit_2(3),
fbit_3 => fbit_3(3)
);
qdr2_qbit_4 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(4),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(4),
fbit_1 => fbit_1(4),
fbit_2 => fbit_2(4),
fbit_3 => fbit_3(4)
);
qdr2_qbit_5 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(5),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(5),
fbit_1 => fbit_1(5),
fbit_2 => fbit_2(5),
fbit_3 => fbit_3(5)
);
qdr2_qbit_6 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(6),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(6),
fbit_1 => fbit_1(6),
fbit_2 => fbit_2(6),
fbit_3 => fbit_3(6)
);
qdr2_qbit_7 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(7),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(7),
fbit_1 => fbit_1(7),
fbit_2 => fbit_2(7),
fbit_3 => fbit_3(7)
);
qdr2_qbit_8 : qdr2_qbit_cq port map
( reset => reset270_r,
cq => cq_delayed_col0(0),
cq1 => cq_delayed_col1(0),
qdr2_q => qdr2_q(8),
CE_R_FB0 => CE_R_FB0,
CE_R_FB1 => CE_R_FB1,
CE_R_FB2 => CE_R_FB2,
CE_R_FB3 => CE_R_FB3,
fbit_0 => fbit_0(8),
fbit_1 => fbit_1(8),
fbit_2 => fbit_2(8),
fbit_3 => fbit_3(8)
);
--****************************************************************************************************************************
RAM_18D_cq0_fbit0 : RAM_18D port map (
A0 => fifo_00_wr_addr(0),
A1 => fifo_00_wr_addr(1),
A2 => fifo_00_wr_addr(2),
A3 => fifo_00_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_00,
D => fbit_0(8 downto 0),
DPO => fifo_00_data_out );
RAM_18D_cq0_fbit1 : RAM_18D port map (
A0 => fifo_01_wr_addr(0),
A1 => fifo_01_wr_addr(1),
A2 => fifo_01_wr_addr(2),
A3 => fifo_01_wr_addr(3),
DPRA0 => fifo_00_rd_addr(0),
DPRA1 => fifo_00_rd_addr(1),
DPRA2 => fifo_00_rd_addr(2),
DPRA3 => fifo_00_rd_addr(3),
WCLK => clk90,
WE => transfer_done_01,
D => fbit_1(8 downto 0),
DPO => fifo_01_data_out );
RAM_18D_cq0_fbit2 : RAM_18D port map (
A0 => fifo_02_wr_addr(0),
A1 => fifo_02_wr_addr(1),
A2 => fifo_02_wr_addr(2),
A3 => fifo_02_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_02,
D => fbit_2(8 downto 0),
DPO => fifo_02_data_out );
RAM_18D_cq0_fbit3 : RAM_18D port map (
A0 => fifo_03_wr_addr(0),
A1 => fifo_03_wr_addr(1),
A2 => fifo_03_wr_addr(2),
A3 => fifo_03_wr_addr(3),
DPRA0 => fifo_02_rd_addr(0),
DPRA1 => fifo_02_rd_addr(1),
DPRA2 => fifo_02_rd_addr(2),
DPRA3 => fifo_02_rd_addr(3),
WCLK => clk90,
WE => transfer_done_03,
D => fbit_3(8 downto 0),
DPO => fifo_03_data_out );
end arc_data_path;
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