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📄 virtex2.v

📁 XILINX memory interface generator. XILINX的外部存储器接口。
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input I2;
parameter INIT = 8'b0;
LUT3 d(O, I0, I1, I2);
defparam d.INIT = INIT;
assign LO=O;
endmodule
module LUT3_L(LO, I0, I1, I2); // synthesis xc_map=lut syn_black_box
output LO;
input I0;
input I1;
input I2;
parameter INIT = 8'b0;
assign LO = I2 ?
     (I1 ? (I0 ? INIT[7] : INIT[6]) : (I0 ? INIT[5] : INIT[4])) : 
     (I1 ? (I0 ? INIT[3] : INIT[2]) : (I0 ? INIT[1] : INIT[0]));
endmodule
module LUT4(O, I0, I1, I2, I3); // synthesis xc_map=lut syn_black_box
output O;
input I0;
input I1;
input I2;
input I3;
parameter INIT = 16'b0;
assign O = I3 ?
    (I2 ?
     (I1 ? (I0 ? INIT[15] : INIT[14]) : (I0 ? INIT[13] : INIT[12])) : 
     (I1 ? (I0 ? INIT[11] : INIT[10]) : (I0 ? INIT[9] : INIT[8]))) :
    (I2 ?
     (I1 ? (I0 ? INIT[7] : INIT[6]) : (I0 ? INIT[5] : INIT[4])) : 
     (I1 ? (I0 ? INIT[3] : INIT[2]) : (I0 ? INIT[1] : INIT[0])));
endmodule
module LUT4_D(O, LO, I0, I1, I2, I3); // synthesis xc_map=lut syn_black_box
output O;
output LO;
input I0;
input I1;
input I2;
input I3;
parameter INIT = 16'b0;
LUT4 d(O, I0, I1, I2, I3);
defparam d.INIT = INIT;
assign LO=O;
endmodule
module LUT4_L(LO, I0, I1, I2, I3); // synthesis xc_map=lut syn_black_box
output LO;
input I0;
input I1;
input I2;
input I3;
parameter INIT = 16'b0;
assign LO = I3 ?
    (I2 ?
     (I1 ? (I0 ? INIT[15] : INIT[14]) : (I0 ? INIT[13] : INIT[12])) : 
     (I1 ? (I0 ? INIT[11] : INIT[10]) : (I0 ? INIT[9] : INIT[8]))) :
    (I2 ?
     (I1 ? (I0 ? INIT[7] : INIT[6]) : (I0 ? INIT[5] : INIT[4])) : 
     (I1 ? (I0 ? INIT[3] : INIT[2]) : (I0 ? INIT[1] : INIT[0])));
endmodule
module MULT18X18 (P, A, B); // synthesis syn_black_box
input  [17:0] A;
input  [17:0] B;
output [35:0] P;
endmodule
module MULT18X18S (P, A, B, C, CE, R); // synthesis syn_black_box
output [35:0] P;
input  [17:0] A;
input  [17:0] B;
input  C;
input  CE;
input  R;
endmodule
module MULT_AND(LO, I0, I1); // synthesis syn_black_box
output LO;
input I0;
input I1;
endmodule
module MUXCY(O, CI, DI, S); // synthesis syn_black_box
output O;
input CI;
input DI;
input S;
endmodule
module MUXCY_D(O, LO, CI, DI, S); // synthesis syn_black_box
output O;
output LO;
input CI;
input DI;
input S;
endmodule
module MUXCY_L(LO, CI, DI, S); // synthesis syn_black_box
output LO;
input CI;
input DI;
input S;
endmodule
module MUXF5(O, I0, I1, S); // synthesis syn_black_box
output O;
input I0;
input I1;
input S;
endmodule
module MUXF5_D(O, LO, I0, I1, S); // synthesis syn_black_box
output O;
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF5_L(LO, I0, I1, S); // synthesis syn_black_box
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF6(O, I0, I1, S); // synthesis syn_black_box
output O;
input I0;
input I1;
input S;
endmodule
module MUXF6_D(O, LO, I0, I1, S); // synthesis syn_black_box
output O;
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF6_L(LO, I0, I1, S); // synthesis syn_black_box
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF7(O, I0, I1, S); // synthesis syn_black_box
output O;
input I0;
input I1;
input S;
endmodule
module MUXF7_D(O, LO, I0, I1, S); // synthesis syn_black_box
output O;
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF7_L(LO, I0, I1, S); // synthesis syn_black_box
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF8(O, I0, I1, S); // synthesis syn_black_box
output O;
input I0;
input I1;
input S;
endmodule
module MUXF8_D(O, LO, I0, I1, S); // synthesis syn_black_box
output O;
output LO;
input I0;
input I1;
input S;
endmodule
module MUXF8_L(LO, I0, I1, S); // synthesis syn_black_box
output LO;
input I0;
input I1;
input S;
endmodule
module OBUF(O, I); // synthesis syn_black_box
parameter IOSTANDARD="default";
parameter SLEW = "SLOW";
parameter DRIVE = 12;
output O;
input I;
endmodule
module OBUFDS(O, OB, I); // synthesis syn_black_box
parameter IOSTANDARD="default";
parameter SLEW = "SLOW";
parameter DRIVE = 12;
output O;
output OB;
input I;
endmodule
module OBUFDS_BLVDS_25(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LDT_25(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LVDSEXT_25(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LVDSEXT_33(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LVDS_25(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LVDS_33(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_ULVDS_25(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LVPECL_25(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFDS_LVPECL_33(O, OB, I); // synthesis syn_black_box
output O;
output OB;
input I;
endmodule
module OBUFT(O, I, T); // synthesis syn_black_box
parameter IOSTANDARD="default";
parameter SLEW = "SLOW";
parameter DRIVE = 12;
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS(O, OB, I, T); // synthesis syn_black_box
parameter IOSTANDARD="default";
parameter SLEW = "SLOW";
parameter DRIVE = 12;
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_BLVDS_25(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LDT_25(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LVDSEXT_25(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LVDSEXT_33(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LVDS_25(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LVDS_33(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_ULVDS_25(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LVPECL_25(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFTDS_LVPECL_33(O, OB, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
output OB /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_AGP(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_12(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_16(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_24(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_4(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_6(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_F_8(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_GTL(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_GTL_DCI(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_GTLP(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_GTLP_DCI(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_I(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_I_DCI(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_II(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_I_18(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_II_18(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_II_DCI(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_III(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_III_DCI(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_IV(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_HSTL_IV_DCI(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_F_12(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_F_16(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_F_2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_F_4(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_F_6(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_F_8(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_S_12(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_S_16(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_S_2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_S_4(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_S_6(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS15_S_8(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_F_12(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_F_16(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_F_2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_F_4(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_F_6(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_F_8(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_S_12(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_S_16(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_S_2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_S_4(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_S_6(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS18_S_8(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS25(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS25_F_12(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS25_F_16(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS25_F_2(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS25_F_24(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
input T;
endmodule
module OBUFT_LVCMOS25_F_4(O, I, T); // synthesis syn_black_box
output O /* synthesis syn_tristate = 1 */;
input I;
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