qdr2_cq_bar_div.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
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// Preparation for data to be sent to the memory

`timescale 1 ns/1 ps

module qdr2_cq_bar_div (cq, cq1, rst_cq_div, cq_tranfert_col1, cq_tranfert_col0);

// Signals
   input 		cq; 			// first column (col0) for negative edge data
   input 		cq1; 			// second column (col1) for positive edge data
   input 		rst_cq_div; 

   output		cq_tranfert_col0;       // col0
   output 		cq_tranfert_col1;       // col1

   wire cqn;
   wire cq1n;

assign cqn = ~cq;
assign cq1n = ~cq1;

// Flip-Flop instantiation

FD col1_transfert ( .Q(cq_tranfert_col0), .C(cq1), .D(rst_cq_div));
FD col0_transfert ( .Q(cq_tranfert_col1), .C(cq), .D(rst_cq_div));
            
endmodule