cq_delay.v

XILINX memory interface generator. XILINX的外部存储器接口。

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// Preparation for data to be sent to the memory

`timescale 1 ns/1 ps

module cq_delay(clk_in,sel_in,clk_out);                                                                     
                                                                                                             
   input       clk_in ;                                                                                      
   input[4:0]  sel_in;                                                                                       
   output      clk_out;                                                                                      
                                                                                                             
   wire        clk_in ;                                                                                      
   wire [4:0]  sel_in;                                                                                       
   wire        clk_out;                                                                                      
                                                                                                             
                                                                                                       
wire delay1 /* synthesis syn_keep = 1 */;                                                                                     
wire delay2 /* synthesis syn_keep = 1 */;                                                                                     
wire delay3 /* synthesis syn_keep = 1 */;                                                                                     
wire delay4 /* synthesis syn_keep = 1 */;                                                                                     
wire delay5 /* synthesis syn_keep = 1 */;                                                                                     
                                                                                          
   LUT4 one( .I0(1'b1), .I1(sel_in[4]), .I2(delay5), .I3(clk_in), .O(clk_out));                              
   defparam    one.INIT = 16'hf3c0;                                                                          
                                                                                                             
   LUT4 two( .I0(clk_in), .I1(sel_in[2]), .I2(1'b1), .I3(delay3), .O(delay4));                               
   defparam    two.INIT = 16'hee22;                                                                          
                                                                                                             
   LUT4 three( .I0(clk_in), .I1(sel_in[0]), .I2(delay1), .I3(1'b1), .O(delay2) );                            
   defparam    three.INIT = 16'he2e2;                                                                        
                                                                                                             
   LUT4 four( .I0(1'b1), .I1(1'b1), .I2(1'b1), .I3(clk_in), .O(delay1) );                                    
   defparam    four.INIT = 16'hff00;                                                                         
                                                                                                             
   LUT4 five( .I0(1'b1), .I1(sel_in[3]), .I2(delay4), .I3(clk_in), .O(delay5) );                             
   defparam    five.INIT = 16'hf3c0;                                                                         
                                                                                                             
   LUT4 six( .I0(clk_in), .I1(sel_in[1]), .I2(delay2), .I3(1'b1), .O(delay3) );                              
   defparam    six.INIT = 16'he2e2;                                                                          
                                                                                                             
                                                                                                             
                                                                                                             
                                                                                                             
                                                                                                             
endmodule