qdr2_reset.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 50 行

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// RESET module (input buffer and signal invertion from PCB)                                                                                                                         

`timescale 1 ns/1 ps

module QDR2_RESET (ML365_RESET, USER_RESET);
                                                                   
 input ML365_RESET;
 output USER_RESET;
 
wire RESET;

assign USER_RESET = ~RESET; // RAKCHOPR - remove IBUF, and move to top level since most designs will have their own reset circuit.
                                    // //Board_inverted_RESET; // Invert this signal as the reset is active low on ML365
                                    
IBUF_LVCMOS25 INST_IBUF (.O(RESET), .I(ML365_RESET));

endmodule