qdr_lc_top.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//** 
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
//**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
//**              provided to you "as is". Xilinx and its licensors make and you 
//**              receive no warranties or conditions, express, implied, statutory 
//**              or otherwise, and Xilinx specifically disclaims any implied 
//**              warranties of merchantability, non-infringement, or fitness for a 
//**              particular purpose. Xilinx does not warrant that the functions 
//**              contained in these designs will meet your requirements, or that the
//**              operation of these designs will be uninterrupted or error free, or 
//**              that defects in the Designs will be corrected. Furthermore, Xilinx 
//**              does not warrant or make any representations regarding use or the 
//**              results of the use of the designs in terms of correctness, accuracy, 
//**              reliability, or otherwise. 
//**
//**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
//**              liable for any loss of data, lost profits, cost or procurement of 
//**              substitute goods or services, or for any special, incidental, 
//**              consequential, or indirect damages arising from the use or operation 
//**              of the designs or accompanying documentation, however caused and on 
//**              any theory of liability. This limitation will apply even if Xilinx 
//**              has been advised of the possibility of such damage. This limitation 
//**              shall apply not-withstanding the failure of the essential purpose of 
//**              any limited remedies herein. 
//**
//*****************************************************************************************

`timescale 1 ns/1 ps

module QDR_LC_TOP(CLK200, CLK200N, Reset, Result_Reg,  mem_D, mem_Q, mem_SA, mem_R_n, mem_W_n, mem_BW_n, mem_K, mem_K_n, mem_C, mem_C_n, mem_CQ, mem_CQ_n, mem_R_n_ext, mem_R_n_int);
   
input CLK200;
input CLK200N;
input Reset;
output Result_Reg;

output [17 : 0] mem_D;
input  [17 : 0] mem_Q;
output [17 : 0] mem_SA;
output mem_R_n;
output mem_W_n;
output [1 : 0] mem_BW_n;
output mem_K;
output mem_K_n;
output mem_C;
output mem_C_n;
input  mem_CQ;
input  mem_CQ_n;
output mem_R_n_ext;
input  mem_R_n_int;


wire [35:0] DataR;
wire [17:0] AddrW;

wire [17:0] AddrW_1int;
wire [17:0] AddrW_2int;
wire [17:0] AddrR; 
wire [17:0] AddrR_FD;
wire FD_UserDataValid;
wire [35:0] FD_Data_R;
wire CLOCK_TEST;
         
wire mem_C; 
wire mem_C_n;
wire [17:0] mem_D; 
wire [17:0] mem_Q; 
wire [17:0] mem_SA; 
wire mem_R_n; 
wire mem_W_n; 
wire [1:0] mem_BW_n; 
wire mem_K; 
wire mem_K_n;
wire mem_CQ; 
wire mem_CQ_n; 

wire UserDataValid;
wire [1:0] Counter_outL;
wire [1:0] Counter_outH;
wire ThisIsAGo;
wire Reset_CLK0;
wire Reset_CLK90;
wire [1:0] To_concatenate;
wire [17:0] Reference_Data;
wire [17:0] FD1_Reference_Data;
wire [17:0] FD2_Reference_Data;
wire [17:0] FD3_Reference_Data;
wire WCtrl_BUF;
wire RCtrl_BUF;
wire DCM_LCK_BUF;
wire D0_capture_BUF;
reg Reference_Data_BUF;

wire [17:0] Cout_WDataL;
wire [17:0] Cout_WDataH;

reg ResetCount;
reg R_n;
reg W_n;
reg Result;
reg Result_BUF;
reg Status_Ctrl_Operation;
reg Status_Ctrl_Operation_buf;

reg [1:0] CurrentState;
reg [1:0] NextState;

parameter Start = 0, GetReady = 1, WriteCycle = 2, ReadCycle = 3;

//*****************************************************************************************
// Pipeline stage for write address
//*****************************************************************************************


FD FD_UDV (.Q(FD_UserDataValid), .D(UserDataValid), .C(GCLK90));  
FD FD_READ_DATA_[35:0] ( .Q(FD_Data_R[35:0]), .D( DataR[35:0]), .C(GCLK90));   


//*****************************************************************************************
// Instantiate QDR-II Memory Interface clocking module
//*****************************************************************************************

qdr2_clocks QDR_interface_clocks (  .USER_CLK(CLK200), 
                            	    .USER_CLK_N(CLK200N),
                            	    .RESET(USER_RESET), 
                            	    .CLK_BUF(CLK_BUF),
                            	    .GCLK0(GCLK0),
                            	    .GCLK90(GCLK90),
                            	    .GCLK180(GCLK180),
                            	    .GCLK270(GCLK270),
			            .CLKDIV2(CLK_DIV2),
			            .LOCKED_DCM(DCM_LOCKED) );


//*****************************************************************************************
// Signal between qdr2_clocks qdr2_burst_4_body
//*****************************************************************************************

wire CLK_BUF;
wire GCLK0;
wire GCLK90;
wire GCLK180;
wire GCLK270;
wire CLK_DIV2;
wire DCM_LOCKED;
     
wire USER_RESET;
reg GCLK0_2;

		
//*****************************************************************************************
// Instantiate QDR-II Memory Interface 
//*****************************************************************************************

qdr2_burst_4_body QDR_Interface_B ( .USER_DWL(Cout_WDataL), 
                                    .USER_DWH(Cout_WDataH),
                                    .USER_Q(DataR), 
                                    .USER_A_READ(AddrR), 
                                    .USER_A_WRITE(AddrW), 
                                    .CLK_BUF(CLK_BUF),
                                    .CLK0E(GCLK0), 
                                    .CLK90E(GCLK90), 
                                    .CLK180E(GCLK180), 
                                    .CLK270E(GCLK270), 
                                    .LOCKED_DCM_PRI(DCM_LOCKED),
                                    .USER_R_n(R_n), 
                                    .USER_W_n(W_n), 
                                    .USER_BW_n(2'b00), 
                                    .USER_RESET(~DCM_LOCKED), 
                                    .USER_DATA_VALID(UserDataValid),
                                    .QDR_Q(mem_Q),
                                    .QDR_D(mem_D),
                                    .QDR_SA(mem_SA),
                                    .QDR_R_n(mem_R_n),
                                    .QDR_W_n(mem_W_n),
                                    .QDR_BW_n(mem_BW_n),
                                    .QDR_K(mem_K),
                                    .QDR_K_n(mem_K_n),
                                    .QDR_C(mem_C),
                                    .QDR_C_n(mem_C_n),
                                    .QDR_CQ(mem_CQ),
                                    .QDR_CQ_n(mem_CQ_n),
                                    .QDR_R_n_ext(mem_R_n_ext),
                                    .QDR_R_n_int(mem_R_n_int),
                                    .TEST_RESET_0(Reset_CLK0));   
                                    
//*****************************************************************************************
// Reset module, specific to ML365 
//*****************************************************************************************                                    
                                                        
QDR2_RESET ML365_RESET (.ML365_RESET(Reset), .USER_RESET(USER_RESET));


assign DCM_LCK_BUF = DCM_LOCKED;

//*****************************************************************************************
// Generate data using a counter, out of CLK0
//*****************************************************************************************                                   
counter_4 WordGene_H0 ( .counter(Counter_outH), 
                         .inclock(GCLK0),
                         .reset(ResetCount))/* synthesis syn_noprune =1 */;   
                     
concat2to36Data Concat_Write_High ( .inclock(GCLK0),
	                            .Sortie(Cout_WDataH),
	                            .counter(Counter_outH))/* synthesis syn_noprune =1 */; 
   	    
counter_4 WordGene_L0 ( .counter(Counter_outL), 
                        .inclock(GCLK0),
                        .reset(ResetCount))/* synthesis syn_noprune =1 */;   
                     
concat2to36Data Concat_Write_Low ( .inclock(GCLK0),
	                           .Sortie(Cout_WDataL),
	                           .counter(Counter_outL))/* synthesis syn_noprune =1 */; 


always@(posedge GCLK0)
if(Reset_CLK0)
GCLK0_2 <= 0;
else 
GCLK0_2 <= ~GCLK0_2;



	                             
//*****************************************************************************************
// Generate addresses using a conter, from address 0, out of CLK0/2 and ~CLK0/2
//*****************************************************************************************  	    

counter_262144 AddrGeneR ( .COut2(AddrR), 
                          .inc(~GCLK0_2),
                          .reset(ResetCount ));   
                          


                          
counter_262144 AddrGeneW ( .COut2(AddrW), //Addr