qdr_lc_top.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//** 
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
//**  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
//**              provided to you "as is". Xilinx and its licensors make and you 
//**              receive no warranties or conditions, express, implied, statutory 
//**              or otherwise, and Xilinx specifically disclaims any implied 
//**              warranties of merchantability, non-infringement, or fitness for a 
//**              particular purpose. Xilinx does not warrant that the functions 
//**              contained in these designs will meet your requirements, or that the
//**              operation of these designs will be uninterrupted or error free, or 
//**              that defects in the Designs will be corrected. Furthermore, Xilinx 
//**              does not warrant or make any representations regarding use or the 
//**              results of the use of the designs in terms of correctness, accuracy, 
//**              reliability, or otherwise. 
//**
//**              LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 
//**              liable for any loss of data, lost profits, cost or procurement of 
//**              substitute goods or services, or for any special, incidental, 
//**              consequential, or indirect damages arising from the use or operation 
//**              of the designs or accompanying documentation, however caused and on 
//**              any theory of liability. This limitation will apply even if Xilinx 
//**              has been advised of the possibility of such damage. This limitation 
//**              shall apply not-withstanding the failure of the essential purpose of 
//**              any limited remedies herein. 
//**
//*****************************************************************************************

`timescale 1 ns/1 ps

module QDR_LC_TOP(CLK200, 
		  CLK200N, 
		  Reset, 
		  GCLK0,
		  GCLK90,
		  GCLK180,
		  GCLK270,
		  Reset_CLK0,
		  Cout_WDataL,
		  Cout_WDataH, 
		  R_n,
		  W_n,
		  DataR,
		  UserDataValid,
		  DCM_LOCKED,
		  sys_rst180,
		  R_n_recapture,
		  mem_D, 
		  mem_Q, 
		  mem_CQ, 
		  mem_CQ_n
);
   
input CLK200;
input CLK200N;
input Reset;
input  [17:0]Cout_WDataL;
input  [17:0]Cout_WDataH; 
input  R_n;
input  W_n;

output [35:0]DataR;
output UserDataValid;
output DCM_LOCKED;
output sys_rst180;
input R_n_recapture;
output GCLK0;
output GCLK90;
output GCLK180;

output GCLK270;

output Reset_CLK0;

output [17 : 0] mem_D;
input  [17 : 0] mem_Q;
input  mem_CQ;
input  mem_CQ_n;

         
wire [17:0] mem_D; 
wire [17:0] mem_Q; 
wire [17:0] mem_SA; 
wire [1:0] mem_BW_n; 
wire mem_C; 
wire mem_C_n;
wire mem_K; 
wire mem_K_n;
wire mem_R_n; 
wire mem_W_n; 

wire mem_CQ; 
wire mem_CQ_n; 




//*****************************************************************************************
// Signal between qdr2_clocks qdr2_burst_4_body
//*****************************************************************************************

wire CLK_BUF;
wire GCLK0;
wire GCLK90;
wire GCLK180;
wire GCLK270;
wire CLK_DIV2;
wire DCM_LOCKED;
     
wire USER_RESET;



//*****************************************************************************************
// Instantiate QDR-II Memory Interface clocking module
//*****************************************************************************************

qdr2_clocks QDR_interface_clocks ( .USER_CLK				(CLK200), 
                            	    		.USER_CLK_N		(CLK200N),
                            	    		.RESET			(USER_RESET), 
                            	    		.CLK_BUF			(CLK_BUF),
                            	    		.GCLK0			(GCLK0),
                            	    		.GCLK90			(GCLK90),
                            	    		.GCLK180			(GCLK180),
                            	    		.GCLK270			(GCLK270),
			           .CLKDIV2			(CLK_DIV2),
			           .LOCKED_DCM		(DCM_LOCKED) );


		
//*****************************************************************************************
// Instantiate QDR-II Memory Interface 
//*****************************************************************************************

qdr2_burst_4_body QDR_Interface_B ( .USER_DWL							(Cout_WDataL), 
                                    .USER_DWH							(Cout_WDataH),
                                    .USER_Q							(DataR), 
                                    .CLK_BUF							(CLK_BUF),
                                    .CLK0E							(GCLK0), 
                                    .CLK90E							(GCLK90), 
                                    .CLK180E							(GCLK180), 
                                    .CLK270E							(GCLK270), 
                                    .R_n_recapture(R_n_recapture),
                                    .LOCKED_DCM_PRI					(DCM_LOCKED),
                                    .USER_R_n							(R_n), 
                                    .USER_W_n							(W_n), 
                                    .USER_RESET							(~DCM_LOCKED), 
                                    .USER_DATA_VALID				(UserDataValid),
                                    .sys_rst180          (sys_rst180),
                                    .QDR_Q							(mem_Q),
                                    .QDR_D							(mem_D),
                                    .QDR_CQ							(mem_CQ),
                                    .QDR_CQ_n							(mem_CQ_n),
                                    .TEST_RESET_0							(Reset_CLK0));   
                                    
//*****************************************************************************************
// Reset module, specific to ML365 
//*****************************************************************************************                                    
                                                        
QDR2_RESET ML365_RESET (.ML365_RESET(Reset), .USER_RESET(USER_RESET));




 
endmodule