data_path.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//**
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
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//*****************************************************************************************
// Description :     This module comprises read data paths for the qdr2 memory interface.                 
//                   The read data is captured in CLB FFs and finally input to FIFOs.
//                     
`timescale 1ns/100ps

module data_path(
	         clk,
	         clk90,
	         clk180,
	         clk270,
	         reset,
	         reset90,
	         reset180,
	         reset270,
	         rst_cq_div,
	         delay_sel,
	         u_data_val,
	         qdr2_cq,
	         qdr2_q,
	         user_output_data
                 );

// Parameters

   parameter data_bits = 18 -1; // Size of the data bus -1
   parameter addr_bits = 18 -1; // Size of the address bus -1
   
                  
   input          clk;
   input          clk90;
   input          clk180;   
   input 	  clk270;
   input 	  reset; 
   input 	  reset90;   
   input 	  reset180;
   input 	  reset270;
   input 	  rst_cq_div;
   input [4:0]    delay_sel;
   input [1:0]    qdr2_cq;
   input [17:0]   qdr2_q;

   output         u_data_val;   
   output [35:0]  user_output_data;
   
reg [35:0]   user_output_data;
   
wire         cq_int_delay_in0;
wire         cq_int_delay_in1;

wire    cq_delayed_col0; // delayed strobe
wire    cq_delayed_col1; // delayed strobe

wire cq_div_transfert_0_col0;
wire cq_div_transfert_0_col1;

wire         transfer_done_00;
wire         transfer_done_01;
wire         transfer_done_02;
wire         transfer_done_03;

wire [17:0]  fbit_0;
wire [17:0]  fbit_1;
wire [17:0]  fbit_2;
wire [17:0]  fbit_3;

wire [17:0]  fifo_00_data_out;
wire [17:0]  fifo_01_data_out;     
wire [17:0]  fifo_02_data_out;     
wire [17:0]  fifo_03_data_out;      


reg [3:0]    fifo_00_wr_addr;
reg [3:0]    fifo_01_wr_addr;
reg [3:0]    fifo_02_wr_addr;
reg [3:0]    fifo_03_wr_addr;

reg [3:0]    fifo_00_rd_addr;
reg [3:0]    fifo_02_rd_addr;


wire         fifo_11_not_empty;
wire         fifo_13_not_empty;

reg          fifo_11_not_empty_r;
reg          fifo_13_not_empty_r;

wire         read_valid_data_1;
wire         read_valid_data_2;
wire         read_valid_data;
reg          rd_data_valid;
reg          next_state;

wire         reset_r;
wire         reset90_r;
wire         reset180_r;
wire         reset270_r;
wire         rst_cq_div_int;
wire         rst_cq_div_reg_fd1;

wire              CE_R_FB0;
wire              CE_R_FB1;
wire              CE_R_FB2;
wire              CE_R_FB3;

assign rst_cq_div_int = ~rst_cq_div;

assign read_valid_data_1 = (fifo_11_not_empty_r && fifo_11_not_empty) ? 1'b1 : 1'b0;

assign read_valid_data_2 = (fifo_13_not_empty_r && fifo_13_not_empty) ? 1'b1 : 1'b0;
                         
assign read_valid_data = read_valid_data_1 || read_valid_data_2;                         

assign u_data_val = rd_data_valid;




assign fifo_11_not_empty = (fifo_00_rd_addr[3:0] == fifo_01_wr_addr[3:0]) ? 1'b0 : 1'b1;                                                                     
assign fifo_13_not_empty = (fifo_02_rd_addr[3:0] == fifo_03_wr_addr[3:0]) ? 1'b0 : 1'b1;

// Write Address incrementation for the read FIFO
always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_00_wr_addr <= 4'h0;
    else if (transfer_done_00 == 1'b1)
      fifo_00_wr_addr <= fifo_00_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_01_wr_addr <= 4'h0;
    else if (transfer_done_01 == 1'b1) 
      fifo_01_wr_addr <= fifo_01_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_02_wr_addr <= 4'h0;
    else if (transfer_done_02 == 1'b1)
      fifo_02_wr_addr <= fifo_02_wr_addr + 1'b1;
end

always @ (posedge clk90)